1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2010,2011 4 * Graeme Russ, <graeme.russ@gmail.com> 5 * 6 * Portions from Coreboot mainboard/google/link/romstage.c 7 * Copyright (C) 2007-2010 coresystems GmbH 8 * Copyright (C) 2011 Google Inc. 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #include <common.h> 14 #include <errno.h> 15 #include <fdtdec.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <rtc.h> 19 #include <spi.h> 20 #include <spi_flash.h> 21 #include <syscon.h> 22 #include <asm/cpu.h> 23 #include <asm/processor.h> 24 #include <asm/gpio.h> 25 #include <asm/global_data.h> 26 #include <asm/intel_regs.h> 27 #include <asm/mrccache.h> 28 #include <asm/mtrr.h> 29 #include <asm/pci.h> 30 #include <asm/report_platform.h> 31 #include <asm/arch/me.h> 32 #include <asm/arch/pei_data.h> 33 #include <asm/arch/pch.h> 34 #include <asm/post.h> 35 #include <asm/arch/sandybridge.h> 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 #define CMOS_OFFSET_MRC_SEED 152 40 #define CMOS_OFFSET_MRC_SEED_S3 156 41 #define CMOS_OFFSET_MRC_SEED_CHK 160 42 43 /* 44 * This function looks for the highest region of memory lower than 4GB which 45 * has enough space for U-Boot where U-Boot is aligned on a page boundary. 46 * It overrides the default implementation found elsewhere which simply 47 * picks the end of ram, wherever that may be. The location of the stack, 48 * the relocation address, and how far U-Boot is moved by relocation are 49 * set in the global data structure. 50 */ 51 ulong board_get_usable_ram_top(ulong total_size) 52 { 53 struct memory_info *info = &gd->arch.meminfo; 54 uintptr_t dest_addr = 0; 55 struct memory_area *largest = NULL; 56 int i; 57 58 /* Find largest area of memory below 4GB */ 59 60 for (i = 0; i < info->num_areas; i++) { 61 struct memory_area *area = &info->area[i]; 62 63 if (area->start >= 1ULL << 32) 64 continue; 65 if (!largest || area->size > largest->size) 66 largest = area; 67 } 68 69 /* If no suitable area was found, return an error. */ 70 assert(largest); 71 if (!largest || largest->size < (2 << 20)) 72 panic("No available memory found for relocation"); 73 74 dest_addr = largest->start + largest->size; 75 76 return (ulong)dest_addr; 77 } 78 79 void dram_init_banksize(void) 80 { 81 struct memory_info *info = &gd->arch.meminfo; 82 int num_banks; 83 int i; 84 85 for (i = 0, num_banks = 0; i < info->num_areas; i++) { 86 struct memory_area *area = &info->area[i]; 87 88 if (area->start >= 1ULL << 32) 89 continue; 90 gd->bd->bi_dram[num_banks].start = area->start; 91 gd->bd->bi_dram[num_banks].size = area->size; 92 num_banks++; 93 } 94 } 95 96 static int read_seed_from_cmos(struct pei_data *pei_data) 97 { 98 u16 c1, c2, checksum, seed_checksum; 99 struct udevice *dev; 100 int ret = 0; 101 102 ret = uclass_get_device(UCLASS_RTC, 0, &dev); 103 if (ret) { 104 debug("Cannot find RTC: err=%d\n", ret); 105 return -ENODEV; 106 } 107 108 /* 109 * Read scrambler seeds from CMOS RAM. We don't want to store them in 110 * SPI flash since they change on every boot and that would wear down 111 * the flash too much. So we store these in CMOS and the large MRC 112 * data in SPI flash. 113 */ 114 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed); 115 if (!ret) { 116 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3, 117 &pei_data->scrambler_seed_s3); 118 } 119 if (ret) { 120 debug("Failed to read from RTC %s\n", dev->name); 121 return ret; 122 } 123 124 debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n", 125 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); 126 debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", 127 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); 128 129 /* Compute seed checksum and compare */ 130 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, 131 sizeof(u32)); 132 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, 133 sizeof(u32)); 134 checksum = add_ip_checksums(sizeof(u32), c1, c2); 135 136 seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK); 137 seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8; 138 139 if (checksum != seed_checksum) { 140 debug("%s: invalid seed checksum\n", __func__); 141 pei_data->scrambler_seed = 0; 142 pei_data->scrambler_seed_s3 = 0; 143 return -EINVAL; 144 } 145 146 return 0; 147 } 148 149 static int prepare_mrc_cache(struct pei_data *pei_data) 150 { 151 struct mrc_data_container *mrc_cache; 152 struct mrc_region entry; 153 int ret; 154 155 ret = read_seed_from_cmos(pei_data); 156 if (ret) 157 return ret; 158 ret = mrccache_get_region(NULL, &entry); 159 if (ret) 160 return ret; 161 mrc_cache = mrccache_find_current(&entry); 162 if (!mrc_cache) 163 return -ENOENT; 164 165 pei_data->mrc_input = mrc_cache->data; 166 pei_data->mrc_input_len = mrc_cache->data_size; 167 debug("%s: at %p, size %x checksum %04x\n", __func__, 168 pei_data->mrc_input, pei_data->mrc_input_len, 169 mrc_cache->checksum); 170 171 return 0; 172 } 173 174 static int write_seeds_to_cmos(struct pei_data *pei_data) 175 { 176 u16 c1, c2, checksum; 177 struct udevice *dev; 178 int ret = 0; 179 180 ret = uclass_get_device(UCLASS_RTC, 0, &dev); 181 if (ret) { 182 debug("Cannot find RTC: err=%d\n", ret); 183 return -ENODEV; 184 } 185 186 /* Save the MRC seed values to CMOS */ 187 rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); 188 debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n", 189 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); 190 191 rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); 192 debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", 193 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); 194 195 /* Save a simple checksum of the seed values */ 196 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, 197 sizeof(u32)); 198 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, 199 sizeof(u32)); 200 checksum = add_ip_checksums(sizeof(u32), c1, c2); 201 202 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff); 203 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff); 204 205 return 0; 206 } 207 208 /* Use this hook to save our SDRAM parameters */ 209 int misc_init_r(void) 210 { 211 int ret; 212 213 ret = mrccache_save(); 214 if (ret) 215 printf("Unable to save MRC data: %d\n", ret); 216 217 return 0; 218 } 219 220 static const char *const ecc_decoder[] = { 221 "inactive", 222 "active on IO", 223 "disabled on IO", 224 "active" 225 }; 226 227 /* 228 * Dump in the log memory controller configuration as read from the memory 229 * controller registers. 230 */ 231 static void report_memory_config(void) 232 { 233 u32 addr_decoder_common, addr_decode_ch[2]; 234 int i; 235 236 addr_decoder_common = readl(MCHBAR_REG(0x5000)); 237 addr_decode_ch[0] = readl(MCHBAR_REG(0x5004)); 238 addr_decode_ch[1] = readl(MCHBAR_REG(0x5008)); 239 240 debug("memcfg DDR3 clock %d MHz\n", 241 (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100); 242 debug("memcfg channel assignment: A: %d, B % d, C % d\n", 243 addr_decoder_common & 3, 244 (addr_decoder_common >> 2) & 3, 245 (addr_decoder_common >> 4) & 3); 246 247 for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { 248 u32 ch_conf = addr_decode_ch[i]; 249 debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf); 250 debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); 251 debug(" enhanced interleave mode %s\n", 252 ((ch_conf >> 22) & 1) ? "on" : "off"); 253 debug(" rank interleave %s\n", 254 ((ch_conf >> 21) & 1) ? "on" : "off"); 255 debug(" DIMMA %d MB width x%d %s rank%s\n", 256 ((ch_conf >> 0) & 0xff) * 256, 257 ((ch_conf >> 19) & 1) ? 16 : 8, 258 ((ch_conf >> 17) & 1) ? "dual" : "single", 259 ((ch_conf >> 16) & 1) ? "" : ", selected"); 260 debug(" DIMMB %d MB width x%d %s rank%s\n", 261 ((ch_conf >> 8) & 0xff) * 256, 262 ((ch_conf >> 20) & 1) ? 16 : 8, 263 ((ch_conf >> 18) & 1) ? "dual" : "single", 264 ((ch_conf >> 16) & 1) ? ", selected" : ""); 265 } 266 } 267 268 static void post_system_agent_init(struct pei_data *pei_data) 269 { 270 /* If PCIe init is skipped, set the PEG clock gating */ 271 if (!pei_data->pcie_init) 272 setbits_le32(MCHBAR_REG(0x7010), 1); 273 } 274 275 static asmlinkage void console_tx_byte(unsigned char byte) 276 { 277 #ifdef DEBUG 278 putc(byte); 279 #endif 280 } 281 282 static int recovery_mode_enabled(void) 283 { 284 return false; 285 } 286 287 /** 288 * Find the PEI executable in the ROM and execute it. 289 * 290 * @dev: Northbridge device 291 * @pei_data: configuration data for UEFI PEI reference code 292 */ 293 int sdram_initialise(struct udevice *dev, struct udevice *me_dev, 294 struct pei_data *pei_data) 295 { 296 unsigned version; 297 const char *data; 298 uint16_t done; 299 int ret; 300 301 report_platform_info(dev); 302 303 /* Wait for ME to be ready */ 304 ret = intel_early_me_init(me_dev); 305 if (ret) 306 return ret; 307 ret = intel_early_me_uma_size(me_dev); 308 if (ret < 0) 309 return ret; 310 311 debug("Starting UEFI PEI System Agent\n"); 312 313 /* 314 * Do not pass MRC data in for recovery mode boot, 315 * Always pass it in for S3 resume. 316 */ 317 if (!recovery_mode_enabled() || 318 pei_data->boot_mode == PEI_BOOT_RESUME) { 319 ret = prepare_mrc_cache(pei_data); 320 if (ret) 321 debug("prepare_mrc_cache failed: %d\n", ret); 322 } 323 324 /* If MRC data is not found we cannot continue S3 resume. */ 325 if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { 326 debug("Giving up in sdram_initialize: No MRC data\n"); 327 reset_cpu(0); 328 } 329 330 /* Pass console handler in pei_data */ 331 pei_data->tx_byte = console_tx_byte; 332 333 debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data)); 334 335 data = (char *)CONFIG_X86_MRC_ADDR; 336 if (data) { 337 int rv; 338 int (*func)(struct pei_data *); 339 ulong start; 340 341 debug("Calling MRC at %p\n", data); 342 post_code(POST_PRE_MRC); 343 start = get_timer(0); 344 func = (int (*)(struct pei_data *))data; 345 rv = func(pei_data); 346 post_code(POST_MRC); 347 if (rv) { 348 switch (rv) { 349 case -1: 350 printf("PEI version mismatch.\n"); 351 break; 352 case -2: 353 printf("Invalid memory frequency.\n"); 354 break; 355 default: 356 printf("MRC returned %x.\n", rv); 357 } 358 printf("Nonzero MRC return value.\n"); 359 return -EFAULT; 360 } 361 debug("MRC execution time %lu ms\n", get_timer(start)); 362 } else { 363 printf("UEFI PEI System Agent not found.\n"); 364 return -ENOSYS; 365 } 366 367 #if CONFIG_USBDEBUG 368 /* mrc.bin reconfigures USB, so reinit it to have debug */ 369 early_usbdebug_init(); 370 #endif 371 372 version = readl(MCHBAR_REG(0x5034)); 373 debug("System Agent Version %d.%d.%d Build %d\n", 374 version >> 24 , (version >> 16) & 0xff, 375 (version >> 8) & 0xff, version & 0xff); 376 debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len, 377 pei_data->mrc_output); 378 379 /* 380 * Send ME init done for SandyBridge here. This is done inside the 381 * SystemAgent binary on IvyBridge 382 */ 383 dm_pci_read_config16(dev, PCI_DEVICE_ID, &done); 384 done &= BASE_REV_MASK; 385 if (BASE_REV_SNB == done) 386 intel_early_me_init_done(dev, me_dev, ME_INIT_STATUS_SUCCESS); 387 else 388 intel_me_status(me_dev); 389 390 post_system_agent_init(pei_data); 391 report_memory_config(); 392 393 /* S3 resume: don't save scrambler seed or MRC data */ 394 if (pei_data->boot_mode != PEI_BOOT_RESUME) { 395 /* 396 * This will be copied to SDRAM in reserve_arch(), then written 397 * to SPI flash in mrccache_save() 398 */ 399 gd->arch.mrc_output = (char *)pei_data->mrc_output; 400 gd->arch.mrc_output_len = pei_data->mrc_output_len; 401 ret = write_seeds_to_cmos(pei_data); 402 if (ret) 403 debug("Failed to write seeds to CMOS: %d\n", ret); 404 } 405 406 return 0; 407 } 408 409 int reserve_arch(void) 410 { 411 return mrccache_reserve(); 412 } 413 414 static int copy_spd(struct pei_data *peid) 415 { 416 const int gpio_vector[] = {41, 42, 43, 10, -1}; 417 int spd_index; 418 const void *blob = gd->fdt_blob; 419 int node, spd_node; 420 int ret, i; 421 422 for (i = 0; ; i++) { 423 if (gpio_vector[i] == -1) 424 break; 425 ret = gpio_requestf(gpio_vector[i], "spd_id%d", i); 426 if (ret) { 427 debug("%s: Could not request gpio %d\n", __func__, 428 gpio_vector[i]); 429 return ret; 430 } 431 } 432 spd_index = gpio_get_values_as_int(gpio_vector); 433 debug("spd index %d\n", spd_index); 434 node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD); 435 if (node < 0) { 436 printf("SPD data not found.\n"); 437 return -ENOENT; 438 } 439 440 for (spd_node = fdt_first_subnode(blob, node); 441 spd_node > 0; 442 spd_node = fdt_next_subnode(blob, spd_node)) { 443 const char *data; 444 int len; 445 446 if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index) 447 continue; 448 data = fdt_getprop(blob, spd_node, "data", &len); 449 if (len < sizeof(peid->spd_data[0])) { 450 printf("Missing SPD data\n"); 451 return -EINVAL; 452 } 453 454 debug("Using SDRAM SPD data for '%s'\n", 455 fdt_get_name(blob, spd_node, NULL)); 456 memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0])); 457 break; 458 } 459 460 if (spd_node < 0) { 461 printf("No SPD data found for index %d\n", spd_index); 462 return -ENOENT; 463 } 464 465 return 0; 466 } 467 468 /** 469 * add_memory_area() - Add a new usable memory area to our list 470 * 471 * Note: @start and @end must not span the first 4GB boundary 472 * 473 * @info: Place to store memory info 474 * @start: Start of this memory area 475 * @end: End of this memory area + 1 476 */ 477 static int add_memory_area(struct memory_info *info, 478 uint64_t start, uint64_t end) 479 { 480 struct memory_area *ptr; 481 482 if (info->num_areas == CONFIG_NR_DRAM_BANKS) 483 return -ENOSPC; 484 485 ptr = &info->area[info->num_areas]; 486 ptr->start = start; 487 ptr->size = end - start; 488 info->total_memory += ptr->size; 489 if (ptr->start < (1ULL << 32)) 490 info->total_32bit_memory += ptr->size; 491 debug("%d: memory %llx size %llx, total now %llx / %llx\n", 492 info->num_areas, ptr->start, ptr->size, 493 info->total_32bit_memory, info->total_memory); 494 info->num_areas++; 495 496 return 0; 497 } 498 499 /** 500 * sdram_find() - Find available memory 501 * 502 * This is a bit complicated since on x86 there are system memory holes all 503 * over the place. We create a list of available memory blocks 504 * 505 * @dev: Northbridge device 506 */ 507 static int sdram_find(struct udevice *dev) 508 { 509 struct memory_info *info = &gd->arch.meminfo; 510 uint32_t tseg_base, uma_size, tolud; 511 uint64_t tom, me_base, touud; 512 uint64_t uma_memory_base = 0; 513 uint64_t uma_memory_size; 514 unsigned long long tomk; 515 uint16_t ggc; 516 u32 val; 517 518 /* Total Memory 2GB example: 519 * 520 * 00000000 0000MB-1992MB 1992MB RAM (writeback) 521 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) 522 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) 523 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) 524 * 7f200000 2034MB TOLUD 525 * 7f800000 2040MB MEBASE 526 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) 527 * 80000000 2048MB TOM 528 * 100000000 4096MB-4102MB 6MB RAM (writeback) 529 * 530 * Total Memory 4GB example: 531 * 532 * 00000000 0000MB-2768MB 2768MB RAM (writeback) 533 * ad000000 2768MB-2776MB 8MB TSEG (SMRR) 534 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) 535 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) 536 * afa00000 2810MB TOLUD 537 * ff800000 4088MB MEBASE 538 * ff800000 4088MB-4096MB 8MB ME UMA (uncached) 539 * 100000000 4096MB TOM 540 * 100000000 4096MB-5374MB 1278MB RAM (writeback) 541 * 14fe00000 5368MB TOUUD 542 */ 543 544 /* Top of Upper Usable DRAM, including remap */ 545 dm_pci_read_config32(dev, TOUUD + 4, &val); 546 touud = (uint64_t)val << 32; 547 dm_pci_read_config32(dev, TOUUD, &val); 548 touud |= val; 549 550 /* Top of Lower Usable DRAM */ 551 dm_pci_read_config32(dev, TOLUD, &tolud); 552 553 /* Top of Memory - does not account for any UMA */ 554 dm_pci_read_config32(dev, 0xa4, &val); 555 tom = (uint64_t)val << 32; 556 dm_pci_read_config32(dev, 0xa0, &val); 557 tom |= val; 558 559 debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom); 560 561 /* ME UMA needs excluding if total memory <4GB */ 562 dm_pci_read_config32(dev, 0x74, &val); 563 me_base = (uint64_t)val << 32; 564 dm_pci_read_config32(dev, 0x70, &val); 565 me_base |= val; 566 567 debug("MEBASE %llx\n", me_base); 568 569 /* TODO: Get rid of all this shifting by 10 bits */ 570 tomk = tolud >> 10; 571 if (me_base == tolud) { 572 /* ME is from MEBASE-TOM */ 573 uma_size = (tom - me_base) >> 10; 574 /* Increment TOLUD to account for ME as RAM */ 575 tolud += uma_size << 10; 576 /* UMA starts at old TOLUD */ 577 uma_memory_base = tomk * 1024ULL; 578 uma_memory_size = uma_size * 1024ULL; 579 debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10); 580 } 581 582 /* Graphics memory comes next */ 583 dm_pci_read_config16(dev, GGC, &ggc); 584 if (!(ggc & 2)) { 585 debug("IGD decoded, subtracting "); 586 587 /* Graphics memory */ 588 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; 589 debug("%uM UMA", uma_size >> 10); 590 tomk -= uma_size; 591 uma_memory_base = tomk * 1024ULL; 592 uma_memory_size += uma_size * 1024ULL; 593 594 /* GTT Graphics Stolen Memory Size (GGMS) */ 595 uma_size = ((ggc >> 8) & 0x3) * 1024ULL; 596 tomk -= uma_size; 597 uma_memory_base = tomk * 1024ULL; 598 uma_memory_size += uma_size * 1024ULL; 599 debug(" and %uM GTT\n", uma_size >> 10); 600 } 601 602 /* Calculate TSEG size from its base which must be below GTT */ 603 dm_pci_read_config32(dev, 0xb8, &tseg_base); 604 uma_size = (uma_memory_base - tseg_base) >> 10; 605 tomk -= uma_size; 606 uma_memory_base = tomk * 1024ULL; 607 uma_memory_size += uma_size * 1024ULL; 608 debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); 609 610 debug("Available memory below 4GB: %lluM\n", tomk >> 10); 611 612 /* Report the memory regions */ 613 add_memory_area(info, 1 << 20, 2 << 28); 614 add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28); 615 add_memory_area(info, (4 << 28) + (2 << 20), tseg_base); 616 add_memory_area(info, 1ULL << 32, touud); 617 618 /* Add MTRRs for memory */ 619 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30); 620 mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20); 621 mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20); 622 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20); 623 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20), 624 32 << 20); 625 626 /* 627 * If >= 4GB installed then memory from TOLUD to 4GB 628 * is remapped above TOM, TOUUD will account for both 629 */ 630 if (touud > (1ULL << 32ULL)) { 631 debug("Available memory above 4GB: %lluM\n", 632 (touud >> 20) - 4096); 633 } 634 635 return 0; 636 } 637 638 static void rcba_config(void) 639 { 640 /* 641 * GFX INTA -> PIRQA (MSI) 642 * D28IP_P3IP WLAN INTA -> PIRQB 643 * D29IP_E1P EHCI1 INTA -> PIRQD 644 * D26IP_E2P EHCI2 INTA -> PIRQF 645 * D31IP_SIP SATA INTA -> PIRQF (MSI) 646 * D31IP_SMIP SMBUS INTB -> PIRQH 647 * D31IP_TTIP THRT INTC -> PIRQA 648 * D27IP_ZIP HDA INTA -> PIRQA (MSI) 649 * 650 * TRACKPAD -> PIRQE (Edge Triggered) 651 * TOUCHSCREEN -> PIRQG (Edge Triggered) 652 */ 653 654 /* Device interrupt pin register (board specific) */ 655 writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | 656 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP)); 657 writel(NOINT << D30IP_PIP, RCB_REG(D30IP)); 658 writel(INTA << D29IP_E1P, RCB_REG(D29IP)); 659 writel(INTA << D28IP_P3IP, RCB_REG(D28IP)); 660 writel(INTA << D27IP_ZIP, RCB_REG(D27IP)); 661 writel(INTA << D26IP_E2P, RCB_REG(D26IP)); 662 writel(NOINT << D25IP_LIP, RCB_REG(D25IP)); 663 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP)); 664 665 /* Device interrupt route registers */ 666 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR)); 667 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR)); 668 writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR)); 669 writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR)); 670 writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR)); 671 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR)); 672 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR)); 673 674 /* Enable IOAPIC (generic) */ 675 writew(0x0100, RCB_REG(OIC)); 676 /* PCH BWG says to read back the IOAPIC enable register */ 677 (void)readw(RCB_REG(OIC)); 678 679 /* Disable unused devices (board specific) */ 680 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS); 681 } 682 683 int dram_init(void) 684 { 685 struct pei_data pei_data __aligned(8) = { 686 .pei_version = PEI_VERSION, 687 .mchbar = MCH_BASE_ADDRESS, 688 .dmibar = DEFAULT_DMIBAR, 689 .epbar = DEFAULT_EPBAR, 690 .pciexbar = CONFIG_PCIE_ECAM_BASE, 691 .smbusbar = SMBUS_IO_BASE, 692 .wdbbar = 0x4000000, 693 .wdbsize = 0x1000, 694 .hpet_address = CONFIG_HPET_ADDRESS, 695 .rcba = DEFAULT_RCBABASE, 696 .pmbase = DEFAULT_PMBASE, 697 .gpiobase = DEFAULT_GPIOBASE, 698 .thermalbase = 0xfed08000, 699 .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ 700 .tseg_size = CONFIG_SMM_TSEG_SIZE, 701 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, 702 .ec_present = 1, 703 .ddr3lv_support = 1, 704 /* 705 * 0 = leave channel enabled 706 * 1 = disable dimm 0 on channel 707 * 2 = disable dimm 1 on channel 708 * 3 = disable dimm 0+1 on channel 709 */ 710 .dimm_channel0_disabled = 2, 711 .dimm_channel1_disabled = 2, 712 .max_ddr3_freq = 1600, 713 .usb_port_config = { 714 /* 715 * Empty and onboard Ports 0-7, set to un-used pin 716 * OC3 717 */ 718 { 0, 3, 0x0000 }, /* P0= Empty */ 719 { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */ 720 { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */ 721 { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */ 722 { 0, 3, 0x0000 }, /* P4= Empty */ 723 { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */ 724 { 0, 3, 0x0000 }, /* P6= Empty */ 725 { 0, 3, 0x0000 }, /* P7= Empty */ 726 /* 727 * Empty and onboard Ports 8-13, set to un-used pin 728 * OC4 729 */ 730 { 1, 4, 0x0040 }, /* P8= Camera (no OC) */ 731 { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */ 732 { 0, 4, 0x0000 }, /* P10= Empty */ 733 { 0, 4, 0x0000 }, /* P11= Empty */ 734 { 0, 4, 0x0000 }, /* P12= Empty */ 735 { 0, 4, 0x0000 }, /* P13= Empty */ 736 }, 737 }; 738 struct udevice *dev, *me_dev; 739 int ret; 740 741 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev); 742 if (ret) 743 return ret; 744 ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev); 745 if (ret) 746 return ret; 747 debug("Boot mode %d\n", gd->arch.pei_boot_mode); 748 debug("mrc_input %p\n", pei_data.mrc_input); 749 pei_data.boot_mode = gd->arch.pei_boot_mode; 750 ret = copy_spd(&pei_data); 751 if (!ret) 752 ret = sdram_initialise(dev, me_dev, &pei_data); 753 if (ret) 754 return ret; 755 756 rcba_config(); 757 quick_ram_check(); 758 759 writew(0xCAFE, MCHBAR_REG(SSKPD)); 760 761 post_code(POST_DRAM); 762 763 ret = sdram_find(dev); 764 if (ret) 765 return ret; 766 767 gd->ram_size = gd->arch.meminfo.total_32bit_memory; 768 769 return 0; 770 } 771