1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2010,2011 4 * Graeme Russ, <graeme.russ@gmail.com> 5 * 6 * Portions from Coreboot mainboard/google/link/romstage.c 7 * Copyright (C) 2007-2010 coresystems GmbH 8 * Copyright (C) 2011 Google Inc. 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #include <common.h> 14 #include <errno.h> 15 #include <fdtdec.h> 16 #include <malloc.h> 17 #include <asm/processor.h> 18 #include <asm/gpio.h> 19 #include <asm/global_data.h> 20 #include <asm/pci.h> 21 #include <asm/arch/me.h> 22 #include <asm/arch/pei_data.h> 23 #include <asm/arch/pch.h> 24 #include <asm/post.h> 25 #include <asm/arch/sandybridge.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 /* 30 * This function looks for the highest region of memory lower than 4GB which 31 * has enough space for U-Boot where U-Boot is aligned on a page boundary. 32 * It overrides the default implementation found elsewhere which simply 33 * picks the end of ram, wherever that may be. The location of the stack, 34 * the relocation address, and how far U-Boot is moved by relocation are 35 * set in the global data structure. 36 */ 37 ulong board_get_usable_ram_top(ulong total_size) 38 { 39 struct memory_info *info = &gd->arch.meminfo; 40 uintptr_t dest_addr = 0; 41 struct memory_area *largest = NULL; 42 int i; 43 44 /* Find largest area of memory below 4GB */ 45 46 for (i = 0; i < info->num_areas; i++) { 47 struct memory_area *area = &info->area[i]; 48 49 if (area->start >= 1ULL << 32) 50 continue; 51 if (!largest || area->size > largest->size) 52 largest = area; 53 } 54 55 /* If no suitable area was found, return an error. */ 56 assert(largest); 57 if (!largest || largest->size < (2 << 20)) 58 panic("No available memory found for relocation"); 59 60 dest_addr = largest->start + largest->size; 61 62 return (ulong)dest_addr; 63 } 64 65 void dram_init_banksize(void) 66 { 67 struct memory_info *info = &gd->arch.meminfo; 68 int num_banks; 69 int i; 70 71 for (i = 0, num_banks = 0; i < info->num_areas; i++) { 72 struct memory_area *area = &info->area[i]; 73 74 if (area->start >= 1ULL << 32) 75 continue; 76 gd->bd->bi_dram[num_banks].start = area->start; 77 gd->bd->bi_dram[num_banks].size = area->size; 78 num_banks++; 79 } 80 } 81 82 static const char *const ecc_decoder[] = { 83 "inactive", 84 "active on IO", 85 "disabled on IO", 86 "active" 87 }; 88 89 /* 90 * Dump in the log memory controller configuration as read from the memory 91 * controller registers. 92 */ 93 static void report_memory_config(void) 94 { 95 u32 addr_decoder_common, addr_decode_ch[2]; 96 int i; 97 98 addr_decoder_common = readl(MCHBAR_REG(0x5000)); 99 addr_decode_ch[0] = readl(MCHBAR_REG(0x5004)); 100 addr_decode_ch[1] = readl(MCHBAR_REG(0x5008)); 101 102 debug("memcfg DDR3 clock %d MHz\n", 103 (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100); 104 debug("memcfg channel assignment: A: %d, B % d, C % d\n", 105 addr_decoder_common & 3, 106 (addr_decoder_common >> 2) & 3, 107 (addr_decoder_common >> 4) & 3); 108 109 for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { 110 u32 ch_conf = addr_decode_ch[i]; 111 debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf); 112 debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); 113 debug(" enhanced interleave mode %s\n", 114 ((ch_conf >> 22) & 1) ? "on" : "off"); 115 debug(" rank interleave %s\n", 116 ((ch_conf >> 21) & 1) ? "on" : "off"); 117 debug(" DIMMA %d MB width x%d %s rank%s\n", 118 ((ch_conf >> 0) & 0xff) * 256, 119 ((ch_conf >> 19) & 1) ? 16 : 8, 120 ((ch_conf >> 17) & 1) ? "dual" : "single", 121 ((ch_conf >> 16) & 1) ? "" : ", selected"); 122 debug(" DIMMB %d MB width x%d %s rank%s\n", 123 ((ch_conf >> 8) & 0xff) * 256, 124 ((ch_conf >> 20) & 1) ? 16 : 8, 125 ((ch_conf >> 18) & 1) ? "dual" : "single", 126 ((ch_conf >> 16) & 1) ? ", selected" : ""); 127 } 128 } 129 130 static void post_system_agent_init(struct pei_data *pei_data) 131 { 132 /* If PCIe init is skipped, set the PEG clock gating */ 133 if (!pei_data->pcie_init) 134 setbits_le32(MCHBAR_REG(0x7010), 1); 135 } 136 137 static asmlinkage void console_tx_byte(unsigned char byte) 138 { 139 #ifdef DEBUG 140 putc(byte); 141 #endif 142 } 143 144 /** 145 * Find the PEI executable in the ROM and execute it. 146 * 147 * @param pei_data: configuration data for UEFI PEI reference code 148 */ 149 int sdram_initialise(struct pei_data *pei_data) 150 { 151 unsigned version; 152 const char *data; 153 uint16_t done; 154 int ret; 155 156 report_platform_info(); 157 158 /* Wait for ME to be ready */ 159 ret = intel_early_me_init(); 160 if (ret) 161 return ret; 162 ret = intel_early_me_uma_size(); 163 if (ret < 0) 164 return ret; 165 166 debug("Starting UEFI PEI System Agent\n"); 167 168 /* If MRC data is not found we cannot continue S3 resume. */ 169 if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { 170 debug("Giving up in sdram_initialize: No MRC data\n"); 171 outb(0x6, PORT_RESET); 172 cpu_hlt(); 173 } 174 175 /* Pass console handler in pei_data */ 176 pei_data->tx_byte = console_tx_byte; 177 178 debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data)); 179 180 data = (char *)CONFIG_X86_MRC_START; 181 if (data) { 182 int rv; 183 int (*func)(struct pei_data *); 184 185 debug("Calling MRC at %p\n", data); 186 post_code(POST_PRE_MRC); 187 func = (int (*)(struct pei_data *))data; 188 rv = func(pei_data); 189 post_code(POST_MRC); 190 if (rv) { 191 switch (rv) { 192 case -1: 193 printf("PEI version mismatch.\n"); 194 break; 195 case -2: 196 printf("Invalid memory frequency.\n"); 197 break; 198 default: 199 printf("MRC returned %x.\n", rv); 200 } 201 printf("Nonzero MRC return value.\n"); 202 return -EFAULT; 203 } 204 } else { 205 printf("UEFI PEI System Agent not found.\n"); 206 return -ENOSYS; 207 } 208 209 #if CONFIG_USBDEBUG 210 /* mrc.bin reconfigures USB, so reinit it to have debug */ 211 early_usbdebug_init(); 212 #endif 213 214 version = readl(MCHBAR_REG(0x5034)); 215 debug("System Agent Version %d.%d.%d Build %d\n", 216 version >> 24 , (version >> 16) & 0xff, 217 (version >> 8) & 0xff, version & 0xff); 218 219 /* 220 * Send ME init done for SandyBridge here. This is done inside the 221 * SystemAgent binary on IvyBridge 222 */ 223 done = pci_read_config32(PCH_DEV, PCI_DEVICE_ID); 224 done &= BASE_REV_MASK; 225 if (BASE_REV_SNB == done) 226 intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); 227 else 228 intel_early_me_status(); 229 230 post_system_agent_init(pei_data); 231 report_memory_config(); 232 233 return 0; 234 } 235 236 static int copy_spd(struct pei_data *peid) 237 { 238 const int gpio_vector[] = {41, 42, 43, 10, -1}; 239 int spd_index; 240 const void *blob = gd->fdt_blob; 241 int node, spd_node; 242 int ret, i; 243 244 for (i = 0; ; i++) { 245 if (gpio_vector[i] == -1) 246 break; 247 ret = gpio_requestf(gpio_vector[i], "spd_id%d", i); 248 if (ret) { 249 debug("%s: Could not request gpio %d\n", __func__, 250 gpio_vector[i]); 251 return ret; 252 } 253 } 254 spd_index = gpio_get_values_as_int(gpio_vector); 255 debug("spd index %d\n", spd_index); 256 node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD); 257 if (node < 0) { 258 printf("SPD data not found.\n"); 259 return -ENOENT; 260 } 261 262 for (spd_node = fdt_first_subnode(blob, node); 263 spd_node > 0; 264 spd_node = fdt_next_subnode(blob, spd_node)) { 265 const char *data; 266 int len; 267 268 if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index) 269 continue; 270 data = fdt_getprop(blob, spd_node, "data", &len); 271 if (len < sizeof(peid->spd_data[0])) { 272 printf("Missing SPD data\n"); 273 return -EINVAL; 274 } 275 276 debug("Using SDRAM SPD data for '%s'\n", 277 fdt_get_name(blob, spd_node, NULL)); 278 memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0])); 279 break; 280 } 281 282 if (spd_node < 0) { 283 printf("No SPD data found for index %d\n", spd_index); 284 return -ENOENT; 285 } 286 287 return 0; 288 } 289 290 /** 291 * add_memory_area() - Add a new usable memory area to our list 292 * 293 * Note: @start and @end must not span the first 4GB boundary 294 * 295 * @info: Place to store memory info 296 * @start: Start of this memory area 297 * @end: End of this memory area + 1 298 */ 299 static int add_memory_area(struct memory_info *info, 300 uint64_t start, uint64_t end) 301 { 302 struct memory_area *ptr; 303 304 if (info->num_areas == CONFIG_NR_DRAM_BANKS) 305 return -ENOSPC; 306 307 ptr = &info->area[info->num_areas]; 308 ptr->start = start; 309 ptr->size = end - start; 310 info->total_memory += ptr->size; 311 if (ptr->start < (1ULL << 32)) 312 info->total_32bit_memory += ptr->size; 313 debug("%d: memory %llx size %llx, total now %llx / %llx\n", 314 info->num_areas, ptr->start, ptr->size, 315 info->total_32bit_memory, info->total_memory); 316 info->num_areas++; 317 318 return 0; 319 } 320 321 /** 322 * sdram_find() - Find available memory 323 * 324 * This is a bit complicated since on x86 there are system memory holes all 325 * over the place. We create a list of available memory blocks 326 */ 327 static int sdram_find(pci_dev_t dev) 328 { 329 struct memory_info *info = &gd->arch.meminfo; 330 uint32_t tseg_base, uma_size, tolud; 331 uint64_t tom, me_base, touud; 332 uint64_t uma_memory_base = 0; 333 uint64_t uma_memory_size; 334 unsigned long long tomk; 335 uint16_t ggc; 336 337 /* Total Memory 2GB example: 338 * 339 * 00000000 0000MB-1992MB 1992MB RAM (writeback) 340 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) 341 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) 342 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) 343 * 7f200000 2034MB TOLUD 344 * 7f800000 2040MB MEBASE 345 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) 346 * 80000000 2048MB TOM 347 * 100000000 4096MB-4102MB 6MB RAM (writeback) 348 * 349 * Total Memory 4GB example: 350 * 351 * 00000000 0000MB-2768MB 2768MB RAM (writeback) 352 * ad000000 2768MB-2776MB 8MB TSEG (SMRR) 353 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) 354 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) 355 * afa00000 2810MB TOLUD 356 * ff800000 4088MB MEBASE 357 * ff800000 4088MB-4096MB 8MB ME UMA (uncached) 358 * 100000000 4096MB TOM 359 * 100000000 4096MB-5374MB 1278MB RAM (writeback) 360 * 14fe00000 5368MB TOUUD 361 */ 362 363 /* Top of Upper Usable DRAM, including remap */ 364 touud = pci_read_config32(dev, TOUUD+4); 365 touud <<= 32; 366 touud |= pci_read_config32(dev, TOUUD); 367 368 /* Top of Lower Usable DRAM */ 369 tolud = pci_read_config32(dev, TOLUD); 370 371 /* Top of Memory - does not account for any UMA */ 372 tom = pci_read_config32(dev, 0xa4); 373 tom <<= 32; 374 tom |= pci_read_config32(dev, 0xa0); 375 376 debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom); 377 378 /* ME UMA needs excluding if total memory <4GB */ 379 me_base = pci_read_config32(dev, 0x74); 380 me_base <<= 32; 381 me_base |= pci_read_config32(dev, 0x70); 382 383 debug("MEBASE %llx\n", me_base); 384 385 /* TODO: Get rid of all this shifting by 10 bits */ 386 tomk = tolud >> 10; 387 if (me_base == tolud) { 388 /* ME is from MEBASE-TOM */ 389 uma_size = (tom - me_base) >> 10; 390 /* Increment TOLUD to account for ME as RAM */ 391 tolud += uma_size << 10; 392 /* UMA starts at old TOLUD */ 393 uma_memory_base = tomk * 1024ULL; 394 uma_memory_size = uma_size * 1024ULL; 395 debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10); 396 } 397 398 /* Graphics memory comes next */ 399 ggc = pci_read_config16(dev, GGC); 400 if (!(ggc & 2)) { 401 debug("IGD decoded, subtracting "); 402 403 /* Graphics memory */ 404 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; 405 debug("%uM UMA", uma_size >> 10); 406 tomk -= uma_size; 407 uma_memory_base = tomk * 1024ULL; 408 uma_memory_size += uma_size * 1024ULL; 409 410 /* GTT Graphics Stolen Memory Size (GGMS) */ 411 uma_size = ((ggc >> 8) & 0x3) * 1024ULL; 412 tomk -= uma_size; 413 uma_memory_base = tomk * 1024ULL; 414 uma_memory_size += uma_size * 1024ULL; 415 debug(" and %uM GTT\n", uma_size >> 10); 416 } 417 418 /* Calculate TSEG size from its base which must be below GTT */ 419 tseg_base = pci_read_config32(dev, 0xb8); 420 uma_size = (uma_memory_base - tseg_base) >> 10; 421 tomk -= uma_size; 422 uma_memory_base = tomk * 1024ULL; 423 uma_memory_size += uma_size * 1024ULL; 424 debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); 425 426 debug("Available memory below 4GB: %lluM\n", tomk >> 10); 427 428 /* Report the memory regions */ 429 add_memory_area(info, 1 << 20, 2 << 28); 430 add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28); 431 add_memory_area(info, (4 << 28) + (2 << 20), tseg_base); 432 add_memory_area(info, 1ULL << 32, touud); 433 /* 434 * If >= 4GB installed then memory from TOLUD to 4GB 435 * is remapped above TOM, TOUUD will account for both 436 */ 437 if (touud > (1ULL << 32ULL)) { 438 debug("Available memory above 4GB: %lluM\n", 439 (touud >> 20) - 4096); 440 } 441 442 return 0; 443 } 444 445 static void rcba_config(void) 446 { 447 /* 448 * GFX INTA -> PIRQA (MSI) 449 * D28IP_P3IP WLAN INTA -> PIRQB 450 * D29IP_E1P EHCI1 INTA -> PIRQD 451 * D26IP_E2P EHCI2 INTA -> PIRQF 452 * D31IP_SIP SATA INTA -> PIRQF (MSI) 453 * D31IP_SMIP SMBUS INTB -> PIRQH 454 * D31IP_TTIP THRT INTC -> PIRQA 455 * D27IP_ZIP HDA INTA -> PIRQA (MSI) 456 * 457 * TRACKPAD -> PIRQE (Edge Triggered) 458 * TOUCHSCREEN -> PIRQG (Edge Triggered) 459 */ 460 461 /* Device interrupt pin register (board specific) */ 462 writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | 463 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP)); 464 writel(NOINT << D30IP_PIP, RCB_REG(D30IP)); 465 writel(INTA << D29IP_E1P, RCB_REG(D29IP)); 466 writel(INTA << D28IP_P3IP, RCB_REG(D28IP)); 467 writel(INTA << D27IP_ZIP, RCB_REG(D27IP)); 468 writel(INTA << D26IP_E2P, RCB_REG(D26IP)); 469 writel(NOINT << D25IP_LIP, RCB_REG(D25IP)); 470 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP)); 471 472 /* Device interrupt route registers */ 473 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR)); 474 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR)); 475 writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR)); 476 writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR)); 477 writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR)); 478 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR)); 479 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR)); 480 481 /* Enable IOAPIC (generic) */ 482 writew(0x0100, RCB_REG(OIC)); 483 /* PCH BWG says to read back the IOAPIC enable register */ 484 (void)readw(RCB_REG(OIC)); 485 486 /* Disable unused devices (board specific) */ 487 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS); 488 } 489 490 int dram_init(void) 491 { 492 struct pei_data pei_data __aligned(8) = { 493 .pei_version = PEI_VERSION, 494 .mchbar = DEFAULT_MCHBAR, 495 .dmibar = DEFAULT_DMIBAR, 496 .epbar = DEFAULT_EPBAR, 497 .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, 498 .smbusbar = SMBUS_IO_BASE, 499 .wdbbar = 0x4000000, 500 .wdbsize = 0x1000, 501 .hpet_address = CONFIG_HPET_ADDRESS, 502 .rcba = DEFAULT_RCBABASE, 503 .pmbase = DEFAULT_PMBASE, 504 .gpiobase = DEFAULT_GPIOBASE, 505 .thermalbase = 0xfed08000, 506 .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ 507 .tseg_size = CONFIG_SMM_TSEG_SIZE, 508 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, 509 .ec_present = 1, 510 .ddr3lv_support = 1, 511 /* 512 * 0 = leave channel enabled 513 * 1 = disable dimm 0 on channel 514 * 2 = disable dimm 1 on channel 515 * 3 = disable dimm 0+1 on channel 516 */ 517 .dimm_channel0_disabled = 2, 518 .dimm_channel1_disabled = 2, 519 .max_ddr3_freq = 1600, 520 .usb_port_config = { 521 /* 522 * Empty and onboard Ports 0-7, set to un-used pin 523 * OC3 524 */ 525 { 0, 3, 0x0000 }, /* P0= Empty */ 526 { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */ 527 { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */ 528 { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */ 529 { 0, 3, 0x0000 }, /* P4= Empty */ 530 { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */ 531 { 0, 3, 0x0000 }, /* P6= Empty */ 532 { 0, 3, 0x0000 }, /* P7= Empty */ 533 /* 534 * Empty and onboard Ports 8-13, set to un-used pin 535 * OC4 536 */ 537 { 1, 4, 0x0040 }, /* P8= Camera (no OC) */ 538 { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */ 539 { 0, 4, 0x0000 }, /* P10= Empty */ 540 { 0, 4, 0x0000 }, /* P11= Empty */ 541 { 0, 4, 0x0000 }, /* P12= Empty */ 542 { 0, 4, 0x0000 }, /* P13= Empty */ 543 }, 544 }; 545 pci_dev_t dev = PCI_BDF(0, 0, 0); 546 int ret; 547 548 debug("Boot mode %d\n", gd->arch.pei_boot_mode); 549 debug("mcr_input %p\n", pei_data.mrc_input); 550 pei_data.boot_mode = gd->arch.pei_boot_mode; 551 ret = copy_spd(&pei_data); 552 if (!ret) 553 ret = sdram_initialise(&pei_data); 554 if (ret) 555 return ret; 556 557 rcba_config(); 558 quick_ram_check(); 559 560 writew(0xCAFE, MCHBAR_REG(SSKPD)); 561 562 post_code(POST_DRAM); 563 564 ret = sdram_find(dev); 565 if (ret) 566 return ret; 567 568 gd->ram_size = gd->arch.meminfo.total_32bit_memory; 569 570 return 0; 571 } 572