1 /* 2 * From Coreboot northbridge/intel/sandybridge/northbridge.c 3 * 4 * Copyright (C) 2007-2009 coresystems GmbH 5 * Copyright (C) 2011 The Chromium Authors 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <asm/msr.h> 13 #include <asm/cpu.h> 14 #include <asm/intel_regs.h> 15 #include <asm/io.h> 16 #include <asm/pci.h> 17 #include <asm/processor.h> 18 #include <asm/arch/pch.h> 19 #include <asm/arch/model_206ax.h> 20 #include <asm/arch/sandybridge.h> 21 22 int bridge_silicon_revision(struct udevice *dev) 23 { 24 struct cpuid_result result; 25 u16 bridge_id; 26 u8 stepping; 27 28 result = cpuid(1); 29 stepping = result.eax & 0xf; 30 dm_pci_read_config16(dev, PCI_DEVICE_ID, &bridge_id); 31 bridge_id &= 0xf0; 32 return bridge_id | stepping; 33 } 34 35 /* 36 * Reserve everything between A segment and 1MB: 37 * 38 * 0xa0000 - 0xbffff: legacy VGA 39 * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) 40 * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI 41 */ 42 static const int legacy_hole_base_k = 0xa0000 / 1024; 43 static const int legacy_hole_size_k = 384; 44 45 static int get_pcie_bar(struct udevice *dev, u32 *base, u32 *len) 46 { 47 u32 pciexbar_reg; 48 49 *base = 0; 50 *len = 0; 51 52 dm_pci_read_config32(dev, PCIEXBAR, &pciexbar_reg); 53 54 if (!(pciexbar_reg & (1 << 0))) 55 return 0; 56 57 switch ((pciexbar_reg >> 1) & 3) { 58 case 0: /* 256MB */ 59 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | 60 (1 << 28)); 61 *len = 256 * 1024 * 1024; 62 return 1; 63 case 1: /* 128M */ 64 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | 65 (1 << 28) | (1 << 27)); 66 *len = 128 * 1024 * 1024; 67 return 1; 68 case 2: /* 64M */ 69 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | 70 (1 << 28) | (1 << 27) | (1 << 26)); 71 *len = 64 * 1024 * 1024; 72 return 1; 73 } 74 75 return 0; 76 } 77 78 static void add_fixed_resources(struct udevice *dev, int index) 79 { 80 u32 pcie_config_base, pcie_config_size; 81 82 if (get_pcie_bar(dev, &pcie_config_base, &pcie_config_size)) { 83 debug("Adding PCIe config bar base=0x%08x size=0x%x\n", 84 pcie_config_base, pcie_config_size); 85 } 86 } 87 88 static void northbridge_dmi_init(struct udevice *dev, int rev) 89 { 90 /* Clear error status bits */ 91 writel(0xffffffff, DMIBAR_REG(0x1c4)); 92 writel(0xffffffff, DMIBAR_REG(0x1d0)); 93 94 /* Steps prior to DMI ASPM */ 95 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { 96 clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20), 97 1 << 21); 98 } 99 100 setbits_le32(DMIBAR_REG(0x238), 1 << 29); 101 102 if (rev >= SNB_STEP_D0) { 103 setbits_le32(DMIBAR_REG(0x1f8), 1 << 16); 104 } else if (rev >= SNB_STEP_D1) { 105 clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16); 106 setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23)); 107 } 108 109 /* Enable ASPM on SNB link, should happen before PCH link */ 110 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) 111 setbits_le32(DMIBAR_REG(0xd04), 1 << 4); 112 113 setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0)); 114 } 115 116 static void northbridge_init(struct udevice *dev, int rev) 117 { 118 u32 bridge_type; 119 120 add_fixed_resources(dev, 6); 121 northbridge_dmi_init(dev, rev); 122 123 bridge_type = readl(MCHBAR_REG(0x5f10)); 124 bridge_type &= ~0xff; 125 126 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) { 127 /* Enable Power Aware Interrupt Routing - fixed priority */ 128 clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4); 129 130 /* 30h for IvyBridge */ 131 bridge_type |= 0x30; 132 } else { 133 /* 20h for Sandybridge */ 134 bridge_type |= 0x20; 135 } 136 writel(bridge_type, MCHBAR_REG(0x5f10)); 137 138 /* 139 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU 140 * that BIOS has initialized memory and power management 141 */ 142 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1); 143 debug("Set BIOS_RESET_CPL\n"); 144 145 /* Configure turbo power limits 1ms after reset complete bit */ 146 mdelay(1); 147 set_power_limits(28); 148 149 /* 150 * CPUs with configurable TDP also need power limits set 151 * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. 152 */ 153 if (cpu_config_tdp_levels()) { 154 msr_t msr = msr_read(MSR_PKG_POWER_LIMIT); 155 156 writel(msr.lo, MCHBAR_REG(0x59A0)); 157 writel(msr.hi, MCHBAR_REG(0x59A4)); 158 } 159 160 /* Set here before graphics PM init */ 161 writel(0x00100001, MCHBAR_REG(0x5500)); 162 } 163 164 static void sandybridge_setup_northbridge_bars(struct udevice *dev) 165 { 166 /* Set up all hardcoded northbridge BARs */ 167 debug("Setting up static registers\n"); 168 dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); 169 dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); 170 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); 171 dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32); 172 /* 64MB - busses 0-63 */ 173 dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); 174 dm_pci_write_config32(dev, PCIEXBAR + 4, 175 (0LL + DEFAULT_PCIEXBAR) >> 32); 176 dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); 177 dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); 178 179 /* Set C0000-FFFFF to access RAM on both reads and writes */ 180 dm_pci_write_config8(dev, PAM0, 0x30); 181 dm_pci_write_config8(dev, PAM1, 0x33); 182 dm_pci_write_config8(dev, PAM2, 0x33); 183 dm_pci_write_config8(dev, PAM3, 0x33); 184 dm_pci_write_config8(dev, PAM4, 0x33); 185 dm_pci_write_config8(dev, PAM5, 0x33); 186 dm_pci_write_config8(dev, PAM6, 0x33); 187 } 188 189 static int bd82x6x_northbridge_early_init(struct udevice *dev) 190 { 191 const int chipset_type = SANDYBRIDGE_MOBILE; 192 u32 capid0_a; 193 u8 reg8; 194 195 /* Device ID Override Enable should be done very early */ 196 dm_pci_read_config32(dev, 0xe4, &capid0_a); 197 if (capid0_a & (1 << 10)) { 198 dm_pci_read_config8(dev, 0xf3, ®8); 199 reg8 &= ~7; /* Clear 2:0 */ 200 201 if (chipset_type == SANDYBRIDGE_MOBILE) 202 reg8 |= 1; /* Set bit 0 */ 203 204 dm_pci_write_config8(dev, 0xf3, reg8); 205 } 206 207 sandybridge_setup_northbridge_bars(dev); 208 209 /* Device Enable */ 210 dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); 211 212 return 0; 213 } 214 215 static int bd82x6x_northbridge_probe(struct udevice *dev) 216 { 217 int rev; 218 219 if (!(gd->flags & GD_FLG_RELOC)) 220 return bd82x6x_northbridge_early_init(dev); 221 222 rev = bridge_silicon_revision(dev); 223 northbridge_init(dev, rev); 224 225 return 0; 226 } 227 228 static const struct udevice_id bd82x6x_northbridge_ids[] = { 229 { .compatible = "intel,bd82x6x-northbridge" }, 230 { } 231 }; 232 233 U_BOOT_DRIVER(bd82x6x_northbridge_drv) = { 234 .name = "bd82x6x_northbridge", 235 .id = UCLASS_NORTHBRIDGE, 236 .of_match = bd82x6x_northbridge_ids, 237 .probe = bd82x6x_northbridge_probe, 238 }; 239