1 /* 2 * From Coreboot northbridge/intel/sandybridge/northbridge.c 3 * 4 * Copyright (C) 2007-2009 coresystems GmbH 5 * Copyright (C) 2011 The Chromium Authors 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <asm/msr.h> 13 #include <asm/cpu.h> 14 #include <asm/intel_regs.h> 15 #include <asm/io.h> 16 #include <asm/pci.h> 17 #include <asm/processor.h> 18 #include <asm/arch/pch.h> 19 #include <asm/arch/model_206ax.h> 20 #include <asm/arch/sandybridge.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 int bridge_silicon_revision(struct udevice *dev) 25 { 26 struct cpuid_result result; 27 u16 bridge_id; 28 u8 stepping; 29 30 result = cpuid(1); 31 stepping = result.eax & 0xf; 32 dm_pci_read_config16(dev, PCI_DEVICE_ID, &bridge_id); 33 bridge_id &= 0xf0; 34 return bridge_id | stepping; 35 } 36 37 static int get_pcie_bar(struct udevice *dev, u32 *base, u32 *len) 38 { 39 u32 pciexbar_reg; 40 41 *base = 0; 42 *len = 0; 43 44 dm_pci_read_config32(dev, PCIEXBAR, &pciexbar_reg); 45 46 if (!(pciexbar_reg & (1 << 0))) 47 return 0; 48 49 switch ((pciexbar_reg >> 1) & 3) { 50 case 0: /* 256MB */ 51 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | 52 (1 << 28)); 53 *len = 256 * 1024 * 1024; 54 return 1; 55 case 1: /* 128M */ 56 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | 57 (1 << 28) | (1 << 27)); 58 *len = 128 * 1024 * 1024; 59 return 1; 60 case 2: /* 64M */ 61 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | 62 (1 << 28) | (1 << 27) | (1 << 26)); 63 *len = 64 * 1024 * 1024; 64 return 1; 65 } 66 67 return 0; 68 } 69 70 static void add_fixed_resources(struct udevice *dev, int index) 71 { 72 u32 pcie_config_base, pcie_config_size; 73 74 if (get_pcie_bar(dev, &pcie_config_base, &pcie_config_size)) { 75 debug("Adding PCIe config bar base=0x%08x size=0x%x\n", 76 pcie_config_base, pcie_config_size); 77 } 78 } 79 80 static void northbridge_dmi_init(struct udevice *dev, int rev) 81 { 82 /* Clear error status bits */ 83 writel(0xffffffff, DMIBAR_REG(0x1c4)); 84 writel(0xffffffff, DMIBAR_REG(0x1d0)); 85 86 /* Steps prior to DMI ASPM */ 87 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { 88 clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20), 89 1 << 21); 90 } 91 92 setbits_le32(DMIBAR_REG(0x238), 1 << 29); 93 94 if (rev >= SNB_STEP_D0) { 95 setbits_le32(DMIBAR_REG(0x1f8), 1 << 16); 96 } else if (rev >= SNB_STEP_D1) { 97 clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16); 98 setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23)); 99 } 100 101 /* Enable ASPM on SNB link, should happen before PCH link */ 102 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) 103 setbits_le32(DMIBAR_REG(0xd04), 1 << 4); 104 105 setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0)); 106 } 107 108 static void northbridge_init(struct udevice *dev, int rev) 109 { 110 u32 bridge_type; 111 112 add_fixed_resources(dev, 6); 113 northbridge_dmi_init(dev, rev); 114 115 bridge_type = readl(MCHBAR_REG(0x5f10)); 116 bridge_type &= ~0xff; 117 118 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) { 119 /* Enable Power Aware Interrupt Routing - fixed priority */ 120 clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4); 121 122 /* 30h for IvyBridge */ 123 bridge_type |= 0x30; 124 } else { 125 /* 20h for Sandybridge */ 126 bridge_type |= 0x20; 127 } 128 writel(bridge_type, MCHBAR_REG(0x5f10)); 129 130 /* 131 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU 132 * that BIOS has initialized memory and power management 133 */ 134 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1); 135 debug("Set BIOS_RESET_CPL\n"); 136 137 /* Configure turbo power limits 1ms after reset complete bit */ 138 mdelay(1); 139 set_power_limits(28); 140 141 /* 142 * CPUs with configurable TDP also need power limits set 143 * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. 144 */ 145 if (cpu_config_tdp_levels()) { 146 msr_t msr = msr_read(MSR_PKG_POWER_LIMIT); 147 148 writel(msr.lo, MCHBAR_REG(0x59A0)); 149 writel(msr.hi, MCHBAR_REG(0x59A4)); 150 } 151 152 /* Set here before graphics PM init */ 153 writel(0x00100001, MCHBAR_REG(0x5500)); 154 } 155 156 static void sandybridge_setup_northbridge_bars(struct udevice *dev) 157 { 158 /* Set up all hardcoded northbridge BARs */ 159 debug("Setting up static registers\n"); 160 dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); 161 dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); 162 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); 163 dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32); 164 /* 64MB - busses 0-63 */ 165 dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); 166 dm_pci_write_config32(dev, PCIEXBAR + 4, 167 (0LL + DEFAULT_PCIEXBAR) >> 32); 168 dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); 169 dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); 170 171 /* Set C0000-FFFFF to access RAM on both reads and writes */ 172 dm_pci_write_config8(dev, PAM0, 0x30); 173 dm_pci_write_config8(dev, PAM1, 0x33); 174 dm_pci_write_config8(dev, PAM2, 0x33); 175 dm_pci_write_config8(dev, PAM3, 0x33); 176 dm_pci_write_config8(dev, PAM4, 0x33); 177 dm_pci_write_config8(dev, PAM5, 0x33); 178 dm_pci_write_config8(dev, PAM6, 0x33); 179 } 180 181 static int bd82x6x_northbridge_early_init(struct udevice *dev) 182 { 183 const int chipset_type = SANDYBRIDGE_MOBILE; 184 u32 capid0_a; 185 u8 reg8; 186 187 /* Device ID Override Enable should be done very early */ 188 dm_pci_read_config32(dev, 0xe4, &capid0_a); 189 if (capid0_a & (1 << 10)) { 190 dm_pci_read_config8(dev, 0xf3, ®8); 191 reg8 &= ~7; /* Clear 2:0 */ 192 193 if (chipset_type == SANDYBRIDGE_MOBILE) 194 reg8 |= 1; /* Set bit 0 */ 195 196 dm_pci_write_config8(dev, 0xf3, reg8); 197 } 198 199 sandybridge_setup_northbridge_bars(dev); 200 201 /* Device Enable */ 202 dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); 203 204 return 0; 205 } 206 207 static int bd82x6x_northbridge_probe(struct udevice *dev) 208 { 209 int rev; 210 211 if (!(gd->flags & GD_FLG_RELOC)) 212 return bd82x6x_northbridge_early_init(dev); 213 214 rev = bridge_silicon_revision(dev); 215 northbridge_init(dev, rev); 216 217 return 0; 218 } 219 220 static const struct udevice_id bd82x6x_northbridge_ids[] = { 221 { .compatible = "intel,bd82x6x-northbridge" }, 222 { } 223 }; 224 225 U_BOOT_DRIVER(bd82x6x_northbridge_drv) = { 226 .name = "bd82x6x_northbridge", 227 .id = UCLASS_NORTHBRIDGE, 228 .of_match = bd82x6x_northbridge_ids, 229 .probe = bd82x6x_northbridge_probe, 230 }; 231