1 /* 2 * From Coreboot northbridge/intel/sandybridge/northbridge.c 3 * 4 * Copyright (C) 2007-2009 coresystems GmbH 5 * Copyright (C) 2011 The Chromium Authors 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #include <common.h> 11 #include <asm/msr.h> 12 #include <asm/acpi.h> 13 #include <asm/cpu.h> 14 #include <asm/io.h> 15 #include <asm/pci.h> 16 #include <asm/processor.h> 17 #include <asm/arch/pch.h> 18 #include <asm/arch/model_206ax.h> 19 #include <asm/arch/sandybridge.h> 20 21 static int bridge_revision_id = -1; 22 23 int bridge_silicon_revision(void) 24 { 25 if (bridge_revision_id < 0) { 26 struct cpuid_result result; 27 uint8_t stepping, bridge_id; 28 pci_dev_t dev; 29 30 result = cpuid(1); 31 stepping = result.eax & 0xf; 32 dev = PCI_BDF(0, 0, 0); 33 bridge_id = pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0; 34 bridge_revision_id = bridge_id | stepping; 35 } 36 37 return bridge_revision_id; 38 } 39 40 /* 41 * Reserve everything between A segment and 1MB: 42 * 43 * 0xa0000 - 0xbffff: legacy VGA 44 * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) 45 * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI 46 */ 47 static const int legacy_hole_base_k = 0xa0000 / 1024; 48 static const int legacy_hole_size_k = 384; 49 50 static int get_pcie_bar(u32 *base, u32 *len) 51 { 52 pci_dev_t dev = PCI_BDF(0, 0, 0); 53 u32 pciexbar_reg; 54 55 *base = 0; 56 *len = 0; 57 58 pciexbar_reg = pci_read_config32(dev, PCIEXBAR); 59 60 if (!(pciexbar_reg & (1 << 0))) 61 return 0; 62 63 switch ((pciexbar_reg >> 1) & 3) { 64 case 0: /* 256MB */ 65 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | 66 (1 << 28)); 67 *len = 256 * 1024 * 1024; 68 return 1; 69 case 1: /* 128M */ 70 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | 71 (1 << 28) | (1 << 27)); 72 *len = 128 * 1024 * 1024; 73 return 1; 74 case 2: /* 64M */ 75 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | 76 (1 << 28) | (1 << 27) | (1 << 26)); 77 *len = 64 * 1024 * 1024; 78 return 1; 79 } 80 81 return 0; 82 } 83 84 static void add_fixed_resources(pci_dev_t dev, int index) 85 { 86 u32 pcie_config_base, pcie_config_size; 87 88 if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { 89 debug("Adding PCIe config bar base=0x%08x size=0x%x\n", 90 pcie_config_base, pcie_config_size); 91 } 92 } 93 94 static void northbridge_dmi_init(pci_dev_t dev) 95 { 96 /* Clear error status bits */ 97 writel(0xffffffff, DMIBAR_REG(0x1c4)); 98 writel(0xffffffff, DMIBAR_REG(0x1d0)); 99 100 /* Steps prior to DMI ASPM */ 101 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { 102 clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20), 103 1 << 21); 104 } 105 106 setbits_le32(DMIBAR_REG(0x238), 1 << 29); 107 108 if (bridge_silicon_revision() >= SNB_STEP_D0) { 109 setbits_le32(DMIBAR_REG(0x1f8), 1 << 16); 110 } else if (bridge_silicon_revision() >= SNB_STEP_D1) { 111 clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16); 112 setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23)); 113 } 114 115 /* Enable ASPM on SNB link, should happen before PCH link */ 116 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) 117 setbits_le32(DMIBAR_REG(0xd04), 1 << 4); 118 119 setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0)); 120 } 121 122 void northbridge_init(pci_dev_t dev) 123 { 124 u32 bridge_type; 125 126 add_fixed_resources(dev, 6); 127 northbridge_dmi_init(dev); 128 129 bridge_type = readl(MCHBAR_REG(0x5f10)); 130 bridge_type &= ~0xff; 131 132 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { 133 /* Enable Power Aware Interrupt Routing - fixed priority */ 134 clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4); 135 136 /* 30h for IvyBridge */ 137 bridge_type |= 0x30; 138 } else { 139 /* 20h for Sandybridge */ 140 bridge_type |= 0x20; 141 } 142 writel(bridge_type, MCHBAR_REG(0x5f10)); 143 144 /* 145 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU 146 * that BIOS has initialized memory and power management 147 */ 148 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1); 149 debug("Set BIOS_RESET_CPL\n"); 150 151 /* Configure turbo power limits 1ms after reset complete bit */ 152 mdelay(1); 153 set_power_limits(28); 154 155 /* 156 * CPUs with configurable TDP also need power limits set 157 * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. 158 */ 159 if (cpu_config_tdp_levels()) { 160 msr_t msr = msr_read(MSR_PKG_POWER_LIMIT); 161 162 writel(msr.lo, MCHBAR_REG(0x59A0)); 163 writel(msr.hi, MCHBAR_REG(0x59A4)); 164 } 165 166 /* Set here before graphics PM init */ 167 writel(0x00100001, MCHBAR_REG(0x5500)); 168 } 169 170 void northbridge_enable(pci_dev_t dev) 171 { 172 #if CONFIG_HAVE_ACPI_RESUME 173 switch (pci_read_config32(dev, SKPAD)) { 174 case 0xcafebabe: 175 debug("Normal boot.\n"); 176 apci_set_slp_type(0); 177 break; 178 case 0xcafed00d: 179 debug("S3 Resume.\n"); 180 apci_set_slp_type(3); 181 break; 182 default: 183 debug("Unknown boot method, assuming normal.\n"); 184 apci_set_slp_type(0); 185 break; 186 } 187 #endif 188 } 189