1 /* 2 * From Coreboot northbridge/intel/sandybridge/northbridge.c 3 * 4 * Copyright (C) 2007-2009 coresystems GmbH 5 * Copyright (C) 2011 The Chromium Authors 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <asm/msr.h> 13 #include <asm/acpi.h> 14 #include <asm/cpu.h> 15 #include <asm/intel_regs.h> 16 #include <asm/io.h> 17 #include <asm/pci.h> 18 #include <asm/processor.h> 19 #include <asm/arch/pch.h> 20 #include <asm/arch/model_206ax.h> 21 #include <asm/arch/sandybridge.h> 22 23 int bridge_silicon_revision(struct udevice *dev) 24 { 25 struct cpuid_result result; 26 u16 bridge_id; 27 u8 stepping; 28 29 result = cpuid(1); 30 stepping = result.eax & 0xf; 31 dm_pci_read_config16(dev, PCI_DEVICE_ID, &bridge_id); 32 bridge_id &= 0xf0; 33 return bridge_id | stepping; 34 } 35 36 /* 37 * Reserve everything between A segment and 1MB: 38 * 39 * 0xa0000 - 0xbffff: legacy VGA 40 * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) 41 * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI 42 */ 43 static const int legacy_hole_base_k = 0xa0000 / 1024; 44 static const int legacy_hole_size_k = 384; 45 46 static int get_pcie_bar(struct udevice *dev, u32 *base, u32 *len) 47 { 48 u32 pciexbar_reg; 49 50 *base = 0; 51 *len = 0; 52 53 dm_pci_read_config32(dev, PCIEXBAR, &pciexbar_reg); 54 55 if (!(pciexbar_reg & (1 << 0))) 56 return 0; 57 58 switch ((pciexbar_reg >> 1) & 3) { 59 case 0: /* 256MB */ 60 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | 61 (1 << 28)); 62 *len = 256 * 1024 * 1024; 63 return 1; 64 case 1: /* 128M */ 65 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | 66 (1 << 28) | (1 << 27)); 67 *len = 128 * 1024 * 1024; 68 return 1; 69 case 2: /* 64M */ 70 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | 71 (1 << 28) | (1 << 27) | (1 << 26)); 72 *len = 64 * 1024 * 1024; 73 return 1; 74 } 75 76 return 0; 77 } 78 79 static void add_fixed_resources(struct udevice *dev, int index) 80 { 81 u32 pcie_config_base, pcie_config_size; 82 83 if (get_pcie_bar(dev, &pcie_config_base, &pcie_config_size)) { 84 debug("Adding PCIe config bar base=0x%08x size=0x%x\n", 85 pcie_config_base, pcie_config_size); 86 } 87 } 88 89 static void northbridge_dmi_init(struct udevice *dev, int rev) 90 { 91 /* Clear error status bits */ 92 writel(0xffffffff, DMIBAR_REG(0x1c4)); 93 writel(0xffffffff, DMIBAR_REG(0x1d0)); 94 95 /* Steps prior to DMI ASPM */ 96 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { 97 clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20), 98 1 << 21); 99 } 100 101 setbits_le32(DMIBAR_REG(0x238), 1 << 29); 102 103 if (rev >= SNB_STEP_D0) { 104 setbits_le32(DMIBAR_REG(0x1f8), 1 << 16); 105 } else if (rev >= SNB_STEP_D1) { 106 clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16); 107 setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23)); 108 } 109 110 /* Enable ASPM on SNB link, should happen before PCH link */ 111 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) 112 setbits_le32(DMIBAR_REG(0xd04), 1 << 4); 113 114 setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0)); 115 } 116 117 static void northbridge_init(struct udevice *dev, int rev) 118 { 119 u32 bridge_type; 120 121 add_fixed_resources(dev, 6); 122 northbridge_dmi_init(dev, rev); 123 124 bridge_type = readl(MCHBAR_REG(0x5f10)); 125 bridge_type &= ~0xff; 126 127 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) { 128 /* Enable Power Aware Interrupt Routing - fixed priority */ 129 clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4); 130 131 /* 30h for IvyBridge */ 132 bridge_type |= 0x30; 133 } else { 134 /* 20h for Sandybridge */ 135 bridge_type |= 0x20; 136 } 137 writel(bridge_type, MCHBAR_REG(0x5f10)); 138 139 /* 140 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU 141 * that BIOS has initialized memory and power management 142 */ 143 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1); 144 debug("Set BIOS_RESET_CPL\n"); 145 146 /* Configure turbo power limits 1ms after reset complete bit */ 147 mdelay(1); 148 set_power_limits(28); 149 150 /* 151 * CPUs with configurable TDP also need power limits set 152 * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. 153 */ 154 if (cpu_config_tdp_levels()) { 155 msr_t msr = msr_read(MSR_PKG_POWER_LIMIT); 156 157 writel(msr.lo, MCHBAR_REG(0x59A0)); 158 writel(msr.hi, MCHBAR_REG(0x59A4)); 159 } 160 161 /* Set here before graphics PM init */ 162 writel(0x00100001, MCHBAR_REG(0x5500)); 163 } 164 165 static void sandybridge_setup_northbridge_bars(struct udevice *dev) 166 { 167 /* Set up all hardcoded northbridge BARs */ 168 debug("Setting up static registers\n"); 169 dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); 170 dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); 171 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); 172 dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32); 173 /* 64MB - busses 0-63 */ 174 dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); 175 dm_pci_write_config32(dev, PCIEXBAR + 4, 176 (0LL + DEFAULT_PCIEXBAR) >> 32); 177 dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); 178 dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); 179 180 /* Set C0000-FFFFF to access RAM on both reads and writes */ 181 dm_pci_write_config8(dev, PAM0, 0x30); 182 dm_pci_write_config8(dev, PAM1, 0x33); 183 dm_pci_write_config8(dev, PAM2, 0x33); 184 dm_pci_write_config8(dev, PAM3, 0x33); 185 dm_pci_write_config8(dev, PAM4, 0x33); 186 dm_pci_write_config8(dev, PAM5, 0x33); 187 dm_pci_write_config8(dev, PAM6, 0x33); 188 } 189 190 static int bd82x6x_northbridge_early_init(struct udevice *dev) 191 { 192 const int chipset_type = SANDYBRIDGE_MOBILE; 193 u32 capid0_a; 194 u8 reg8; 195 196 /* Device ID Override Enable should be done very early */ 197 dm_pci_read_config32(dev, 0xe4, &capid0_a); 198 if (capid0_a & (1 << 10)) { 199 dm_pci_read_config8(dev, 0xf3, ®8); 200 reg8 &= ~7; /* Clear 2:0 */ 201 202 if (chipset_type == SANDYBRIDGE_MOBILE) 203 reg8 |= 1; /* Set bit 0 */ 204 205 dm_pci_write_config8(dev, 0xf3, reg8); 206 } 207 208 sandybridge_setup_northbridge_bars(dev); 209 210 /* Device Enable */ 211 dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); 212 213 return 0; 214 } 215 216 static int bd82x6x_northbridge_probe(struct udevice *dev) 217 { 218 int rev; 219 220 if (!(gd->flags & GD_FLG_RELOC)) 221 return bd82x6x_northbridge_early_init(dev); 222 223 rev = bridge_silicon_revision(dev); 224 northbridge_init(dev, rev); 225 226 return 0; 227 } 228 229 static const struct udevice_id bd82x6x_northbridge_ids[] = { 230 { .compatible = "intel,bd82x6x-northbridge" }, 231 { } 232 }; 233 234 U_BOOT_DRIVER(bd82x6x_northbridge_drv) = { 235 .name = "bd82x6x_northbridge", 236 .id = UCLASS_NORTHBRIDGE, 237 .of_match = bd82x6x_northbridge_ids, 238 .probe = bd82x6x_northbridge_probe, 239 }; 240