1 /* 2 * From coreboot southbridge/intel/bd82x6x/lpc.c 3 * 4 * Copyright (C) 2008-2009 coresystems GmbH 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <fdtdec.h> 13 #include <rtc.h> 14 #include <pci.h> 15 #include <asm/acpi.h> 16 #include <asm/interrupt.h> 17 #include <asm/io.h> 18 #include <asm/ioapic.h> 19 #include <asm/pci.h> 20 #include <asm/arch/pch.h> 21 22 #define NMI_OFF 0 23 24 #define ENABLE_ACPI_MODE_IN_COREBOOT 0 25 #define TEST_SMM_FLASH_LOCKDOWN 0 26 27 static int pch_enable_apic(struct udevice *pch) 28 { 29 u32 reg32; 30 int i; 31 32 /* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */ 33 dm_pci_write_config8(pch, ACPI_CNTL, 0x80); 34 35 writel(0, IO_APIC_INDEX); 36 writel(1 << 25, IO_APIC_DATA); 37 38 /* affirm full set of redirection table entries ("write once") */ 39 writel(1, IO_APIC_INDEX); 40 reg32 = readl(IO_APIC_DATA); 41 writel(1, IO_APIC_INDEX); 42 writel(reg32, IO_APIC_DATA); 43 44 writel(0, IO_APIC_INDEX); 45 reg32 = readl(IO_APIC_DATA); 46 debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f); 47 if (reg32 != (1 << 25)) { 48 printf("APIC Error - cannot write to registers\n"); 49 return -EPERM; 50 } 51 52 debug("Dumping IOAPIC registers\n"); 53 for (i = 0; i < 3; i++) { 54 writel(i, IO_APIC_INDEX); 55 debug(" reg 0x%04x:", i); 56 reg32 = readl(IO_APIC_DATA); 57 debug(" 0x%08x\n", reg32); 58 } 59 60 /* Select Boot Configuration register. */ 61 writel(3, IO_APIC_INDEX); 62 63 /* Use Processor System Bus to deliver interrupts. */ 64 writel(1, IO_APIC_DATA); 65 66 return 0; 67 } 68 69 static void pch_enable_serial_irqs(struct udevice *pch) 70 { 71 u32 value; 72 73 /* Set packet length and toggle silent mode bit for one frame. */ 74 value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0); 75 #ifdef CONFIG_SERIRQ_CONTINUOUS_MODE 76 dm_pci_write_config8(pch, SERIRQ_CNTL, value); 77 #else 78 dm_pci_write_config8(pch, SERIRQ_CNTL, value | (1 << 6)); 79 #endif 80 } 81 82 static int pch_pirq_init(struct udevice *pch) 83 { 84 uint8_t route[8], *ptr; 85 86 if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset, 87 "intel,pirq-routing", route, sizeof(route))) 88 return -EINVAL; 89 ptr = route; 90 dm_pci_write_config8(pch, PIRQA_ROUT, *ptr++); 91 dm_pci_write_config8(pch, PIRQB_ROUT, *ptr++); 92 dm_pci_write_config8(pch, PIRQC_ROUT, *ptr++); 93 dm_pci_write_config8(pch, PIRQD_ROUT, *ptr++); 94 95 dm_pci_write_config8(pch, PIRQE_ROUT, *ptr++); 96 dm_pci_write_config8(pch, PIRQF_ROUT, *ptr++); 97 dm_pci_write_config8(pch, PIRQG_ROUT, *ptr++); 98 dm_pci_write_config8(pch, PIRQH_ROUT, *ptr++); 99 100 /* 101 * TODO(sjg@chromium.org): U-Boot does not set up the interrupts 102 * here. It's unclear if it is needed 103 */ 104 return 0; 105 } 106 107 static int pch_gpi_routing(struct udevice *pch) 108 { 109 u8 route[16]; 110 u32 reg; 111 int gpi; 112 113 if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset, 114 "intel,gpi-routing", route, sizeof(route))) 115 return -EINVAL; 116 117 for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++) 118 reg |= route[gpi] << (gpi * 2); 119 120 dm_pci_write_config32(pch, 0xb8, reg); 121 122 return 0; 123 } 124 125 static int pch_power_options(struct udevice *pch) 126 { 127 const void *blob = gd->fdt_blob; 128 int node = pch->of_offset; 129 u8 reg8; 130 u16 reg16, pmbase; 131 u32 reg32; 132 const char *state; 133 int pwr_on; 134 int nmi_option; 135 int ret; 136 137 /* 138 * Which state do we want to goto after g3 (power restored)? 139 * 0 == S0 Full On 140 * 1 == S5 Soft Off 141 * 142 * If the option is not existent (Laptops), use Kconfig setting. 143 * TODO(sjg@chromium.org): Make this configurable 144 */ 145 pwr_on = MAINBOARD_POWER_ON; 146 147 dm_pci_read_config16(pch, GEN_PMCON_3, ®16); 148 reg16 &= 0xfffe; 149 switch (pwr_on) { 150 case MAINBOARD_POWER_OFF: 151 reg16 |= 1; 152 state = "off"; 153 break; 154 case MAINBOARD_POWER_ON: 155 reg16 &= ~1; 156 state = "on"; 157 break; 158 case MAINBOARD_POWER_KEEP: 159 reg16 &= ~1; 160 state = "state keep"; 161 break; 162 default: 163 state = "undefined"; 164 } 165 166 reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ 167 reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ 168 169 reg16 &= ~(1 << 10); 170 reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ 171 172 reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ 173 174 dm_pci_write_config16(pch, GEN_PMCON_3, reg16); 175 debug("Set power %s after power failure.\n", state); 176 177 /* Set up NMI on errors. */ 178 reg8 = inb(0x61); 179 reg8 &= 0x0f; /* Higher Nibble must be 0 */ 180 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ 181 reg8 |= (1 << 2); /* PCI SERR# Disable for now */ 182 outb(reg8, 0x61); 183 184 reg8 = inb(0x70); 185 /* TODO(sjg@chromium.org): Make this configurable */ 186 nmi_option = NMI_OFF; 187 if (nmi_option) { 188 debug("NMI sources enabled.\n"); 189 reg8 &= ~(1 << 7); /* Set NMI. */ 190 } else { 191 debug("NMI sources disabled.\n"); 192 /* Can't mask NMI from PCI-E and NMI_NOW */ 193 reg8 |= (1 << 7); 194 } 195 outb(reg8, 0x70); 196 197 /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ 198 dm_pci_read_config16(pch, GEN_PMCON_1, ®16); 199 reg16 &= ~(3 << 0); /* SMI# rate 1 minute */ 200 reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ 201 #if DEBUG_PERIODIC_SMIS 202 /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */ 203 reg16 |= (3 << 0); /* Periodic SMI every 8s */ 204 #endif 205 dm_pci_write_config16(pch, GEN_PMCON_1, reg16); 206 207 /* Set the board's GPI routing. */ 208 ret = pch_gpi_routing(pch); 209 if (ret) 210 return ret; 211 212 dm_pci_read_config16(pch, 0x40, &pmbase); 213 pmbase &= 0xfffe; 214 215 writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node, 216 "intel,gpe0-enable", 0)); 217 writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node, 218 "intel,alt-gp-smi-enable", 0)); 219 220 /* Set up power management block and determine sleep mode */ 221 reg32 = inl(pmbase + 0x04); /* PM1_CNT */ 222 reg32 &= ~(7 << 10); /* SLP_TYP */ 223 reg32 |= (1 << 0); /* SCI_EN */ 224 outl(reg32, pmbase + 0x04); 225 226 /* Clear magic status bits to prevent unexpected wake */ 227 setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0)); 228 clrbits_le32(RCB_REG(0x3f02), 0xf); 229 230 return 0; 231 } 232 233 static void pch_rtc_init(struct udevice *pch) 234 { 235 int rtc_failed; 236 u8 reg8; 237 238 dm_pci_read_config8(pch, GEN_PMCON_3, ®8); 239 rtc_failed = reg8 & RTC_BATTERY_DEAD; 240 if (rtc_failed) { 241 reg8 &= ~RTC_BATTERY_DEAD; 242 dm_pci_write_config8(pch, GEN_PMCON_3, reg8); 243 } 244 debug("rtc_failed = 0x%x\n", rtc_failed); 245 246 /* TODO: Handle power failure */ 247 if (rtc_failed) 248 printf("RTC power failed\n"); 249 } 250 251 /* CougarPoint PCH Power Management init */ 252 static void cpt_pm_init(struct udevice *pch) 253 { 254 debug("CougarPoint PM init\n"); 255 dm_pci_write_config8(pch, 0xa9, 0x47); 256 setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0)); 257 258 setbits_le32(RCB_REG(0x228c), 1 << 0); 259 setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14)); 260 setbits_le32(RCB_REG(0x0900), 1 << 14); 261 writel(0xc0388400, RCB_REG(0x2304)); 262 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); 263 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); 264 clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf); 265 writel(0x050f0000, RCB_REG(0x3318)); 266 writel(0x04000000, RCB_REG(0x3324)); 267 setbits_le32(RCB_REG(0x3340), 0xfffff); 268 setbits_le32(RCB_REG(0x3344), 1 << 1); 269 270 writel(0x0001c000, RCB_REG(0x3360)); 271 writel(0x00061100, RCB_REG(0x3368)); 272 writel(0x7f8fdfff, RCB_REG(0x3378)); 273 writel(0x000003fc, RCB_REG(0x337c)); 274 writel(0x00001000, RCB_REG(0x3388)); 275 writel(0x0001c000, RCB_REG(0x3390)); 276 writel(0x00000800, RCB_REG(0x33a0)); 277 writel(0x00001000, RCB_REG(0x33b0)); 278 writel(0x00093900, RCB_REG(0x33c0)); 279 writel(0x24653002, RCB_REG(0x33cc)); 280 writel(0x062108fe, RCB_REG(0x33d0)); 281 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); 282 writel(0x01010000, RCB_REG(0x3a28)); 283 writel(0x01010404, RCB_REG(0x3a2c)); 284 writel(0x01041041, RCB_REG(0x3a80)); 285 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); 286 setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */ 287 setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */ 288 writel(0x00000001, RCB_REG(0x3a6c)); 289 clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c); 290 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); 291 writel(0, RCB_REG(0x33c8)); 292 setbits_le32(RCB_REG(0x21b0), 0xf); 293 } 294 295 /* PantherPoint PCH Power Management init */ 296 static void ppt_pm_init(struct udevice *pch) 297 { 298 debug("PantherPoint PM init\n"); 299 dm_pci_write_config8(pch, 0xa9, 0x47); 300 setbits_le32(RCB_REG(0x2238), 1 << 0); 301 setbits_le32(RCB_REG(0x228c), 1 << 0); 302 setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14)); 303 setbits_le16(RCB_REG(0x0900), 1 << 14); 304 writel(0xc03b8400, RCB_REG(0x2304)); 305 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); 306 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); 307 clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf); 308 writel(0x054f0000, RCB_REG(0x3318)); 309 writel(0x04000000, RCB_REG(0x3324)); 310 setbits_le32(RCB_REG(0x3340), 0xfffff); 311 setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0)); 312 writel(0x0001c000, RCB_REG(0x3360)); 313 writel(0x00061100, RCB_REG(0x3368)); 314 writel(0x7f8fdfff, RCB_REG(0x3378)); 315 writel(0x000003fd, RCB_REG(0x337c)); 316 writel(0x00001000, RCB_REG(0x3388)); 317 writel(0x0001c000, RCB_REG(0x3390)); 318 writel(0x00000800, RCB_REG(0x33a0)); 319 writel(0x00001000, RCB_REG(0x33b0)); 320 writel(0x00093900, RCB_REG(0x33c0)); 321 writel(0x24653002, RCB_REG(0x33cc)); 322 writel(0x067388fe, RCB_REG(0x33d0)); 323 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); 324 writel(0x01010000, RCB_REG(0x3a28)); 325 writel(0x01010404, RCB_REG(0x3a2c)); 326 writel(0x01040000, RCB_REG(0x3a80)); 327 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); 328 /* SATA 2/3 disabled */ 329 setbits_le32(RCB_REG(0x3a84), 1 << 24); 330 /* SATA 4/5 disabled */ 331 setbits_le32(RCB_REG(0x3a88), 1 << 0); 332 writel(0x00000001, RCB_REG(0x3a6c)); 333 clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c); 334 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); 335 setbits_le32(RCB_REG(0x33a4), (1 << 0)); 336 writel(0, RCB_REG(0x33c8)); 337 setbits_le32(RCB_REG(0x21b0), 0xf); 338 } 339 340 static void enable_hpet(void) 341 { 342 /* Move HPET to default address 0xfed00000 and enable it */ 343 clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7); 344 } 345 346 static void enable_clock_gating(struct udevice *pch) 347 { 348 u32 reg32; 349 u16 reg16; 350 351 setbits_le32(RCB_REG(0x2234), 0xf); 352 353 dm_pci_read_config16(pch, GEN_PMCON_1, ®16); 354 reg16 |= (1 << 2) | (1 << 11); 355 dm_pci_write_config16(pch, GEN_PMCON_1, reg16); 356 357 pch_iobp_update(pch, 0xEB007F07, ~0UL, (1 << 31)); 358 pch_iobp_update(pch, 0xEB004000, ~0UL, (1 << 7)); 359 pch_iobp_update(pch, 0xEC007F07, ~0UL, (1 << 31)); 360 pch_iobp_update(pch, 0xEC004000, ~0UL, (1 << 7)); 361 362 reg32 = readl(RCB_REG(CG)); 363 reg32 |= (1 << 31); 364 reg32 |= (1 << 29) | (1 << 28); 365 reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); 366 reg32 |= (1 << 16); 367 reg32 |= (1 << 17); 368 reg32 |= (1 << 18); 369 reg32 |= (1 << 22); 370 reg32 |= (1 << 23); 371 reg32 &= ~(1 << 20); 372 reg32 |= (1 << 19); 373 reg32 |= (1 << 0); 374 reg32 |= (0xf << 1); 375 writel(reg32, RCB_REG(CG)); 376 377 setbits_le32(RCB_REG(0x38c0), 0x7); 378 setbits_le32(RCB_REG(0x36d4), 0x6680c004); 379 setbits_le32(RCB_REG(0x3564), 0x3); 380 } 381 382 static void pch_disable_smm_only_flashing(struct udevice *pch) 383 { 384 u8 reg8; 385 386 debug("Enabling BIOS updates outside of SMM... "); 387 dm_pci_read_config8(pch, 0xdc, ®8); /* BIOS_CNTL */ 388 reg8 &= ~(1 << 5); 389 dm_pci_write_config8(pch, 0xdc, reg8); 390 } 391 392 static void pch_fixups(struct udevice *pch) 393 { 394 u8 gen_pmcon_2; 395 396 /* Indicate DRAM init done for MRC S3 to know it can resume */ 397 dm_pci_read_config8(pch, GEN_PMCON_2, &gen_pmcon_2); 398 gen_pmcon_2 |= (1 << 7); 399 dm_pci_write_config8(pch, GEN_PMCON_2, gen_pmcon_2); 400 401 /* Enable DMI ASPM in the PCH */ 402 clrbits_le32(RCB_REG(0x2304), 1 << 10); 403 setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10)); 404 setbits_le32(RCB_REG(0x21a8), 0x3); 405 } 406 407 /* 408 * Enable Prefetching and Caching. 409 */ 410 static void enable_spi_prefetch(struct udevice *pch) 411 { 412 u8 reg8; 413 414 dm_pci_read_config8(pch, 0xdc, ®8); 415 reg8 &= ~(3 << 2); 416 reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ 417 dm_pci_write_config8(pch, 0xdc, reg8); 418 } 419 420 static void enable_port80_on_lpc(struct udevice *pch) 421 { 422 /* Enable port 80 POST on LPC */ 423 dm_pci_write_config32(pch, PCH_RCBA_BASE, DEFAULT_RCBA | 1); 424 clrbits_le32(RCB_REG(GCS), 4); 425 } 426 427 static void set_spi_speed(void) 428 { 429 u32 fdod; 430 431 /* Observe SPI Descriptor Component Section 0 */ 432 writel(0x1000, RCB_REG(SPI_DESC_COMP0)); 433 434 /* Extract the1 Write/Erase SPI Frequency from descriptor */ 435 fdod = readl(RCB_REG(SPI_FREQ_WR_ERA)); 436 fdod >>= 24; 437 fdod &= 7; 438 439 /* Set Software Sequence frequency to match */ 440 clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod); 441 } 442 443 /** 444 * lpc_early_init() - set up LPC serial ports and other early things 445 * 446 * @dev: LPC device 447 * @return 0 if OK, -ve on error 448 */ 449 static int lpc_early_init(struct udevice *dev) 450 { 451 struct reg_info { 452 u32 base; 453 u32 size; 454 } values[4], *ptr; 455 int count; 456 int i; 457 458 count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset, 459 "intel,gen-dec", (u32 *)values, 460 sizeof(values) / sizeof(u32)); 461 if (count < 0) 462 return -EINVAL; 463 464 /* Set COM1/COM2 decode range */ 465 dm_pci_write_config16(dev->parent, LPC_IO_DEC, 0x0010); 466 467 /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ 468 dm_pci_write_config16(dev->parent, LPC_EN, KBC_LPC_EN | MC_LPC_EN | 469 GAMEL_LPC_EN | COMA_LPC_EN); 470 471 /* Write all registers but use 0 if we run out of data */ 472 count = count * sizeof(u32) / sizeof(values[0]); 473 for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) { 474 u32 reg = 0; 475 476 if (i < count) 477 reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16); 478 dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg); 479 } 480 481 enable_spi_prefetch(dev->parent); 482 483 /* This is already done in start.S, but let's do it in C */ 484 enable_port80_on_lpc(dev->parent); 485 486 set_spi_speed(); 487 488 return 0; 489 } 490 491 static int lpc_init_extra(struct udevice *dev) 492 { 493 struct udevice *pch = dev->parent; 494 const void *blob = gd->fdt_blob; 495 int node; 496 497 debug("pch: lpc_init\n"); 498 dm_pci_write_bar32(pch, 0, 0); 499 dm_pci_write_bar32(pch, 1, 0xff800000); 500 dm_pci_write_bar32(pch, 2, 0xfec00000); 501 dm_pci_write_bar32(pch, 3, 0x800); 502 dm_pci_write_bar32(pch, 4, 0x900); 503 504 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); 505 if (node < 0) 506 return -ENOENT; 507 508 /* Set the value for PCI command register. */ 509 dm_pci_write_config16(pch, PCI_COMMAND, 0x000f); 510 511 /* IO APIC initialization. */ 512 pch_enable_apic(pch); 513 514 pch_enable_serial_irqs(pch); 515 516 /* Setup the PIRQ. */ 517 pch_pirq_init(pch); 518 519 /* Setup power options. */ 520 pch_power_options(pch); 521 522 /* Initialize power management */ 523 switch (pch_silicon_type(pch)) { 524 case PCH_TYPE_CPT: /* CougarPoint */ 525 cpt_pm_init(pch); 526 break; 527 case PCH_TYPE_PPT: /* PantherPoint */ 528 ppt_pm_init(pch); 529 break; 530 default: 531 printf("Unknown Chipset: %s\n", pch->name); 532 return -ENOSYS; 533 } 534 535 /* Initialize the real time clock. */ 536 pch_rtc_init(pch); 537 538 /* Initialize the High Precision Event Timers, if present. */ 539 enable_hpet(); 540 541 /* Initialize Clock Gating */ 542 enable_clock_gating(pch); 543 544 pch_disable_smm_only_flashing(pch); 545 546 pch_fixups(pch); 547 548 return 0; 549 } 550 551 static int bd82x6x_lpc_early_init(struct udevice *dev) 552 { 553 /* Setting up Southbridge. In the northbridge code. */ 554 debug("Setting up static southbridge registers\n"); 555 dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, DEFAULT_RCBA | 1); 556 dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1); 557 558 /* Enable ACPI BAR */ 559 dm_pci_write_config8(dev->parent, ACPI_CNTL, 0x80); 560 561 debug("Disabling watchdog reboot\n"); 562 setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ 563 outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ 564 565 dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1); 566 dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10); 567 568 return 0; 569 } 570 571 static int bd82x6x_lpc_probe(struct udevice *dev) 572 { 573 int ret; 574 575 if (!(gd->flags & GD_FLG_RELOC)) { 576 ret = lpc_early_init(dev); 577 if (ret) { 578 debug("%s: lpc_early_init() failed\n", __func__); 579 return ret; 580 } 581 582 return bd82x6x_lpc_early_init(dev); 583 } 584 585 return lpc_init_extra(dev); 586 } 587 588 static const struct udevice_id bd82x6x_lpc_ids[] = { 589 { .compatible = "intel,bd82x6x-lpc" }, 590 { } 591 }; 592 593 U_BOOT_DRIVER(bd82x6x_lpc_drv) = { 594 .name = "lpc", 595 .id = UCLASS_LPC, 596 .of_match = bd82x6x_lpc_ids, 597 .probe = bd82x6x_lpc_probe, 598 }; 599