1 /* 2 * From coreboot southbridge/intel/bd82x6x/lpc.c 3 * 4 * Copyright (C) 2008-2009 coresystems GmbH 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <fdtdec.h> 13 #include <rtc.h> 14 #include <pci.h> 15 #include <asm/intel_regs.h> 16 #include <asm/interrupt.h> 17 #include <asm/io.h> 18 #include <asm/ioapic.h> 19 #include <asm/lpc_common.h> 20 #include <asm/pci.h> 21 #include <asm/arch/pch.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define NMI_OFF 0 26 27 #define ENABLE_ACPI_MODE_IN_COREBOOT 0 28 #define TEST_SMM_FLASH_LOCKDOWN 0 29 30 static int pch_enable_apic(struct udevice *pch) 31 { 32 u32 reg32; 33 int i; 34 35 /* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */ 36 dm_pci_write_config8(pch, ACPI_CNTL, 0x80); 37 38 writel(0, IO_APIC_INDEX); 39 writel(1 << 25, IO_APIC_DATA); 40 41 /* affirm full set of redirection table entries ("write once") */ 42 writel(1, IO_APIC_INDEX); 43 reg32 = readl(IO_APIC_DATA); 44 writel(1, IO_APIC_INDEX); 45 writel(reg32, IO_APIC_DATA); 46 47 writel(0, IO_APIC_INDEX); 48 reg32 = readl(IO_APIC_DATA); 49 debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f); 50 if (reg32 != (1 << 25)) { 51 printf("APIC Error - cannot write to registers\n"); 52 return -EPERM; 53 } 54 55 debug("Dumping IOAPIC registers\n"); 56 for (i = 0; i < 3; i++) { 57 writel(i, IO_APIC_INDEX); 58 debug(" reg 0x%04x:", i); 59 reg32 = readl(IO_APIC_DATA); 60 debug(" 0x%08x\n", reg32); 61 } 62 63 /* Select Boot Configuration register. */ 64 writel(3, IO_APIC_INDEX); 65 66 /* Use Processor System Bus to deliver interrupts. */ 67 writel(1, IO_APIC_DATA); 68 69 return 0; 70 } 71 72 static void pch_enable_serial_irqs(struct udevice *pch) 73 { 74 u32 value; 75 76 /* Set packet length and toggle silent mode bit for one frame. */ 77 value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0); 78 #ifdef CONFIG_SERIRQ_CONTINUOUS_MODE 79 dm_pci_write_config8(pch, SERIRQ_CNTL, value); 80 #else 81 dm_pci_write_config8(pch, SERIRQ_CNTL, value | (1 << 6)); 82 #endif 83 } 84 85 static int pch_pirq_init(struct udevice *pch) 86 { 87 uint8_t route[8], *ptr; 88 89 if (fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(pch), 90 "intel,pirq-routing", route, sizeof(route))) 91 return -EINVAL; 92 ptr = route; 93 dm_pci_write_config8(pch, PIRQA_ROUT, *ptr++); 94 dm_pci_write_config8(pch, PIRQB_ROUT, *ptr++); 95 dm_pci_write_config8(pch, PIRQC_ROUT, *ptr++); 96 dm_pci_write_config8(pch, PIRQD_ROUT, *ptr++); 97 98 dm_pci_write_config8(pch, PIRQE_ROUT, *ptr++); 99 dm_pci_write_config8(pch, PIRQF_ROUT, *ptr++); 100 dm_pci_write_config8(pch, PIRQG_ROUT, *ptr++); 101 dm_pci_write_config8(pch, PIRQH_ROUT, *ptr++); 102 103 /* 104 * TODO(sjg@chromium.org): U-Boot does not set up the interrupts 105 * here. It's unclear if it is needed 106 */ 107 return 0; 108 } 109 110 static int pch_gpi_routing(struct udevice *pch) 111 { 112 u8 route[16]; 113 u32 reg; 114 int gpi; 115 116 if (fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(pch), 117 "intel,gpi-routing", route, sizeof(route))) 118 return -EINVAL; 119 120 for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++) 121 reg |= route[gpi] << (gpi * 2); 122 123 dm_pci_write_config32(pch, 0xb8, reg); 124 125 return 0; 126 } 127 128 static int pch_power_options(struct udevice *pch) 129 { 130 const void *blob = gd->fdt_blob; 131 int node = dev_of_offset(pch); 132 u8 reg8; 133 u16 reg16, pmbase; 134 u32 reg32; 135 const char *state; 136 int pwr_on; 137 int nmi_option; 138 int ret; 139 140 /* 141 * Which state do we want to goto after g3 (power restored)? 142 * 0 == S0 Full On 143 * 1 == S5 Soft Off 144 * 145 * If the option is not existent (Laptops), use Kconfig setting. 146 * TODO(sjg@chromium.org): Make this configurable 147 */ 148 pwr_on = MAINBOARD_POWER_ON; 149 150 dm_pci_read_config16(pch, GEN_PMCON_3, ®16); 151 reg16 &= 0xfffe; 152 switch (pwr_on) { 153 case MAINBOARD_POWER_OFF: 154 reg16 |= 1; 155 state = "off"; 156 break; 157 case MAINBOARD_POWER_ON: 158 reg16 &= ~1; 159 state = "on"; 160 break; 161 case MAINBOARD_POWER_KEEP: 162 reg16 &= ~1; 163 state = "state keep"; 164 break; 165 default: 166 state = "undefined"; 167 } 168 169 reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ 170 reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ 171 172 reg16 &= ~(1 << 10); 173 reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ 174 175 reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ 176 177 dm_pci_write_config16(pch, GEN_PMCON_3, reg16); 178 debug("Set power %s after power failure.\n", state); 179 180 /* Set up NMI on errors. */ 181 reg8 = inb(0x61); 182 reg8 &= 0x0f; /* Higher Nibble must be 0 */ 183 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ 184 reg8 |= (1 << 2); /* PCI SERR# Disable for now */ 185 outb(reg8, 0x61); 186 187 reg8 = inb(0x70); 188 /* TODO(sjg@chromium.org): Make this configurable */ 189 nmi_option = NMI_OFF; 190 if (nmi_option) { 191 debug("NMI sources enabled.\n"); 192 reg8 &= ~(1 << 7); /* Set NMI. */ 193 } else { 194 debug("NMI sources disabled.\n"); 195 /* Can't mask NMI from PCI-E and NMI_NOW */ 196 reg8 |= (1 << 7); 197 } 198 outb(reg8, 0x70); 199 200 /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ 201 dm_pci_read_config16(pch, GEN_PMCON_1, ®16); 202 reg16 &= ~(3 << 0); /* SMI# rate 1 minute */ 203 reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ 204 #if DEBUG_PERIODIC_SMIS 205 /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */ 206 reg16 |= (3 << 0); /* Periodic SMI every 8s */ 207 #endif 208 dm_pci_write_config16(pch, GEN_PMCON_1, reg16); 209 210 /* Set the board's GPI routing. */ 211 ret = pch_gpi_routing(pch); 212 if (ret) 213 return ret; 214 215 dm_pci_read_config16(pch, 0x40, &pmbase); 216 pmbase &= 0xfffe; 217 218 writel(fdtdec_get_int(blob, node, "intel,gpe0-enable", 0), 219 (ulong)pmbase + GPE0_EN); 220 writew(fdtdec_get_int(blob, node, "intel,alt-gp-smi-enable", 0), 221 (ulong)pmbase + ALT_GP_SMI_EN); 222 223 /* Set up power management block and determine sleep mode */ 224 reg32 = inl(pmbase + 0x04); /* PM1_CNT */ 225 reg32 &= ~(7 << 10); /* SLP_TYP */ 226 reg32 |= (1 << 0); /* SCI_EN */ 227 outl(reg32, pmbase + 0x04); 228 229 /* Clear magic status bits to prevent unexpected wake */ 230 setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0)); 231 clrbits_le32(RCB_REG(0x3f02), 0xf); 232 233 return 0; 234 } 235 236 static void pch_rtc_init(struct udevice *pch) 237 { 238 int rtc_failed; 239 u8 reg8; 240 241 dm_pci_read_config8(pch, GEN_PMCON_3, ®8); 242 rtc_failed = reg8 & RTC_BATTERY_DEAD; 243 if (rtc_failed) { 244 reg8 &= ~RTC_BATTERY_DEAD; 245 dm_pci_write_config8(pch, GEN_PMCON_3, reg8); 246 } 247 debug("rtc_failed = 0x%x\n", rtc_failed); 248 249 /* TODO: Handle power failure */ 250 if (rtc_failed) 251 printf("RTC power failed\n"); 252 } 253 254 /* CougarPoint PCH Power Management init */ 255 static void cpt_pm_init(struct udevice *pch) 256 { 257 debug("CougarPoint PM init\n"); 258 dm_pci_write_config8(pch, 0xa9, 0x47); 259 setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0)); 260 261 setbits_le32(RCB_REG(0x228c), 1 << 0); 262 setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14)); 263 setbits_le32(RCB_REG(0x0900), 1 << 14); 264 writel(0xc0388400, RCB_REG(0x2304)); 265 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); 266 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); 267 clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf); 268 writel(0x050f0000, RCB_REG(0x3318)); 269 writel(0x04000000, RCB_REG(0x3324)); 270 setbits_le32(RCB_REG(0x3340), 0xfffff); 271 setbits_le32(RCB_REG(0x3344), 1 << 1); 272 273 writel(0x0001c000, RCB_REG(0x3360)); 274 writel(0x00061100, RCB_REG(0x3368)); 275 writel(0x7f8fdfff, RCB_REG(0x3378)); 276 writel(0x000003fc, RCB_REG(0x337c)); 277 writel(0x00001000, RCB_REG(0x3388)); 278 writel(0x0001c000, RCB_REG(0x3390)); 279 writel(0x00000800, RCB_REG(0x33a0)); 280 writel(0x00001000, RCB_REG(0x33b0)); 281 writel(0x00093900, RCB_REG(0x33c0)); 282 writel(0x24653002, RCB_REG(0x33cc)); 283 writel(0x062108fe, RCB_REG(0x33d0)); 284 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); 285 writel(0x01010000, RCB_REG(0x3a28)); 286 writel(0x01010404, RCB_REG(0x3a2c)); 287 writel(0x01041041, RCB_REG(0x3a80)); 288 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); 289 setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */ 290 setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */ 291 writel(0x00000001, RCB_REG(0x3a6c)); 292 clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c); 293 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); 294 writel(0, RCB_REG(0x33c8)); 295 setbits_le32(RCB_REG(0x21b0), 0xf); 296 } 297 298 /* PantherPoint PCH Power Management init */ 299 static void ppt_pm_init(struct udevice *pch) 300 { 301 debug("PantherPoint PM init\n"); 302 dm_pci_write_config8(pch, 0xa9, 0x47); 303 setbits_le32(RCB_REG(0x2238), 1 << 0); 304 setbits_le32(RCB_REG(0x228c), 1 << 0); 305 setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14)); 306 setbits_le16(RCB_REG(0x0900), 1 << 14); 307 writel(0xc03b8400, RCB_REG(0x2304)); 308 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); 309 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); 310 clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf); 311 writel(0x054f0000, RCB_REG(0x3318)); 312 writel(0x04000000, RCB_REG(0x3324)); 313 setbits_le32(RCB_REG(0x3340), 0xfffff); 314 setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0)); 315 writel(0x0001c000, RCB_REG(0x3360)); 316 writel(0x00061100, RCB_REG(0x3368)); 317 writel(0x7f8fdfff, RCB_REG(0x3378)); 318 writel(0x000003fd, RCB_REG(0x337c)); 319 writel(0x00001000, RCB_REG(0x3388)); 320 writel(0x0001c000, RCB_REG(0x3390)); 321 writel(0x00000800, RCB_REG(0x33a0)); 322 writel(0x00001000, RCB_REG(0x33b0)); 323 writel(0x00093900, RCB_REG(0x33c0)); 324 writel(0x24653002, RCB_REG(0x33cc)); 325 writel(0x067388fe, RCB_REG(0x33d0)); 326 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); 327 writel(0x01010000, RCB_REG(0x3a28)); 328 writel(0x01010404, RCB_REG(0x3a2c)); 329 writel(0x01040000, RCB_REG(0x3a80)); 330 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); 331 /* SATA 2/3 disabled */ 332 setbits_le32(RCB_REG(0x3a84), 1 << 24); 333 /* SATA 4/5 disabled */ 334 setbits_le32(RCB_REG(0x3a88), 1 << 0); 335 writel(0x00000001, RCB_REG(0x3a6c)); 336 clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c); 337 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); 338 setbits_le32(RCB_REG(0x33a4), (1 << 0)); 339 writel(0, RCB_REG(0x33c8)); 340 setbits_le32(RCB_REG(0x21b0), 0xf); 341 } 342 343 static void enable_hpet(void) 344 { 345 /* Move HPET to default address 0xfed00000 and enable it */ 346 clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7); 347 } 348 349 static void enable_clock_gating(struct udevice *pch) 350 { 351 u32 reg32; 352 u16 reg16; 353 354 setbits_le32(RCB_REG(0x2234), 0xf); 355 356 dm_pci_read_config16(pch, GEN_PMCON_1, ®16); 357 reg16 |= (1 << 2) | (1 << 11); 358 dm_pci_write_config16(pch, GEN_PMCON_1, reg16); 359 360 pch_iobp_update(pch, 0xeb007f07, ~0U, 1 << 31); 361 pch_iobp_update(pch, 0xeb004000, ~0U, 1 << 7); 362 pch_iobp_update(pch, 0xec007f07, ~0U, 1 << 31); 363 pch_iobp_update(pch, 0xec004000, ~0U, 1 << 7); 364 365 reg32 = readl(RCB_REG(CG)); 366 reg32 |= (1 << 31); 367 reg32 |= (1 << 29) | (1 << 28); 368 reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); 369 reg32 |= (1 << 16); 370 reg32 |= (1 << 17); 371 reg32 |= (1 << 18); 372 reg32 |= (1 << 22); 373 reg32 |= (1 << 23); 374 reg32 &= ~(1 << 20); 375 reg32 |= (1 << 19); 376 reg32 |= (1 << 0); 377 reg32 |= (0xf << 1); 378 writel(reg32, RCB_REG(CG)); 379 380 setbits_le32(RCB_REG(0x38c0), 0x7); 381 setbits_le32(RCB_REG(0x36d4), 0x6680c004); 382 setbits_le32(RCB_REG(0x3564), 0x3); 383 } 384 385 static void pch_disable_smm_only_flashing(struct udevice *pch) 386 { 387 u8 reg8; 388 389 debug("Enabling BIOS updates outside of SMM... "); 390 dm_pci_read_config8(pch, 0xdc, ®8); /* BIOS_CNTL */ 391 reg8 &= ~(1 << 5); 392 dm_pci_write_config8(pch, 0xdc, reg8); 393 } 394 395 static void pch_fixups(struct udevice *pch) 396 { 397 u8 gen_pmcon_2; 398 399 /* Indicate DRAM init done for MRC S3 to know it can resume */ 400 dm_pci_read_config8(pch, GEN_PMCON_2, &gen_pmcon_2); 401 gen_pmcon_2 |= (1 << 7); 402 dm_pci_write_config8(pch, GEN_PMCON_2, gen_pmcon_2); 403 404 /* Enable DMI ASPM in the PCH */ 405 clrbits_le32(RCB_REG(0x2304), 1 << 10); 406 setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10)); 407 setbits_le32(RCB_REG(0x21a8), 0x3); 408 } 409 410 static void set_spi_speed(void) 411 { 412 u32 fdod; 413 414 /* Observe SPI Descriptor Component Section 0 */ 415 writel(0x1000, RCB_REG(SPI_DESC_COMP0)); 416 417 /* Extract the1 Write/Erase SPI Frequency from descriptor */ 418 fdod = readl(RCB_REG(SPI_FREQ_WR_ERA)); 419 fdod >>= 24; 420 fdod &= 7; 421 422 /* Set Software Sequence frequency to match */ 423 clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod); 424 } 425 426 static int lpc_init_extra(struct udevice *dev) 427 { 428 struct udevice *pch = dev->parent; 429 430 debug("pch: lpc_init\n"); 431 dm_pci_write_bar32(pch, 0, 0); 432 dm_pci_write_bar32(pch, 1, 0xff800000); 433 dm_pci_write_bar32(pch, 2, 0xfec00000); 434 dm_pci_write_bar32(pch, 3, 0x800); 435 dm_pci_write_bar32(pch, 4, 0x900); 436 437 /* Set the value for PCI command register. */ 438 dm_pci_write_config16(pch, PCI_COMMAND, 0x000f); 439 440 /* IO APIC initialization. */ 441 pch_enable_apic(pch); 442 443 pch_enable_serial_irqs(pch); 444 445 /* Setup the PIRQ. */ 446 pch_pirq_init(pch); 447 448 /* Setup power options. */ 449 pch_power_options(pch); 450 451 /* Initialize power management */ 452 switch (pch_silicon_type(pch)) { 453 case PCH_TYPE_CPT: /* CougarPoint */ 454 cpt_pm_init(pch); 455 break; 456 case PCH_TYPE_PPT: /* PantherPoint */ 457 ppt_pm_init(pch); 458 break; 459 default: 460 printf("Unknown Chipset: %s\n", pch->name); 461 return -ENOSYS; 462 } 463 464 /* Initialize the real time clock. */ 465 pch_rtc_init(pch); 466 467 /* Initialize the High Precision Event Timers, if present. */ 468 enable_hpet(); 469 470 /* Initialize Clock Gating */ 471 enable_clock_gating(pch); 472 473 pch_disable_smm_only_flashing(pch); 474 475 pch_fixups(pch); 476 477 return 0; 478 } 479 480 static int bd82x6x_lpc_early_init(struct udevice *dev) 481 { 482 set_spi_speed(); 483 484 /* Setting up Southbridge. In the northbridge code. */ 485 debug("Setting up static southbridge registers\n"); 486 dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, 487 RCB_BASE_ADDRESS | 1); 488 dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1); 489 490 /* Enable ACPI BAR */ 491 dm_pci_write_config8(dev->parent, ACPI_CNTL, 0x80); 492 493 debug("Disabling watchdog reboot\n"); 494 setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ 495 outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ 496 497 dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1); 498 dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10); 499 500 return 0; 501 } 502 503 static int bd82x6x_lpc_probe(struct udevice *dev) 504 { 505 int ret; 506 507 if (!(gd->flags & GD_FLG_RELOC)) { 508 ret = lpc_common_early_init(dev); 509 if (ret) { 510 debug("%s: lpc_early_init() failed\n", __func__); 511 return ret; 512 } 513 514 return bd82x6x_lpc_early_init(dev); 515 } 516 517 return lpc_init_extra(dev); 518 } 519 520 static const struct udevice_id bd82x6x_lpc_ids[] = { 521 { .compatible = "intel,bd82x6x-lpc" }, 522 { } 523 }; 524 525 U_BOOT_DRIVER(bd82x6x_lpc_drv) = { 526 .name = "lpc", 527 .id = UCLASS_LPC, 528 .of_match = bd82x6x_lpc_ids, 529 .probe = bd82x6x_lpc_probe, 530 }; 531