1 /* 2 * Copyright (c) 2014 Google, Inc 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * Some portions from coreboot src/mainboard/google/link/romstage.c 7 * and src/cpu/intel/model_206ax/bootblock.c 8 * Copyright (C) 2007-2010 coresystems GmbH 9 * Copyright (C) 2011 Google Inc. 10 * 11 * SPDX-License-Identifier: GPL-2.0 12 */ 13 14 #include <common.h> 15 #include <dm.h> 16 #include <errno.h> 17 #include <fdtdec.h> 18 #include <pch.h> 19 #include <asm/cpu.h> 20 #include <asm/io.h> 21 #include <asm/lapic.h> 22 #include <asm/msr.h> 23 #include <asm/mtrr.h> 24 #include <asm/pci.h> 25 #include <asm/post.h> 26 #include <asm/processor.h> 27 #include <asm/arch/model_206ax.h> 28 #include <asm/arch/microcode.h> 29 #include <asm/arch/pch.h> 30 #include <asm/arch/sandybridge.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 static int set_flex_ratio_to_tdp_nominal(void) 35 { 36 msr_t flex_ratio, msr; 37 u8 nominal_ratio; 38 39 /* Minimum CPU revision for configurable TDP support */ 40 if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) 41 return -EINVAL; 42 43 /* Check for Flex Ratio support */ 44 flex_ratio = msr_read(MSR_FLEX_RATIO); 45 if (!(flex_ratio.lo & FLEX_RATIO_EN)) 46 return -EINVAL; 47 48 /* Check for >0 configurable TDPs */ 49 msr = msr_read(MSR_PLATFORM_INFO); 50 if (((msr.hi >> 1) & 3) == 0) 51 return -EINVAL; 52 53 /* Use nominal TDP ratio for flex ratio */ 54 msr = msr_read(MSR_CONFIG_TDP_NOMINAL); 55 nominal_ratio = msr.lo & 0xff; 56 57 /* See if flex ratio is already set to nominal TDP ratio */ 58 if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) 59 return 0; 60 61 /* Set flex ratio to nominal TDP ratio */ 62 flex_ratio.lo &= ~0xff00; 63 flex_ratio.lo |= nominal_ratio << 8; 64 flex_ratio.lo |= FLEX_RATIO_LOCK; 65 msr_write(MSR_FLEX_RATIO, flex_ratio); 66 67 /* Set flex ratio in soft reset data register bits 11:6 */ 68 clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6, 69 (nominal_ratio & 0x3f) << 6); 70 71 /* Set soft reset control to use register value */ 72 setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1); 73 74 /* Issue warm reset, will be "CPU only" due to soft reset data */ 75 outb(0x0, PORT_RESET); 76 outb(SYS_RST | RST_CPU, PORT_RESET); 77 cpu_hlt(); 78 79 /* Not reached */ 80 return -EINVAL; 81 } 82 83 int arch_cpu_init(void) 84 { 85 post_code(POST_CPU_INIT); 86 87 return x86_cpu_init_f(); 88 } 89 90 int arch_cpu_init_dm(void) 91 { 92 struct pci_controller *hose; 93 struct udevice *bus, *dev; 94 int ret; 95 96 post_code(0x70); 97 ret = uclass_get_device(UCLASS_PCI, 0, &bus); 98 post_code(0x71); 99 if (ret) 100 return ret; 101 post_code(0x72); 102 hose = dev_get_uclass_priv(bus); 103 104 /* TODO(sjg@chromium.org): Get rid of gd->hose */ 105 gd->hose = hose; 106 107 ret = uclass_first_device(UCLASS_LPC, &dev); 108 if (!dev) 109 return -ENODEV; 110 111 /* 112 * We should do as little as possible before the serial console is 113 * up. Perhaps this should move to later. Our next lot of init 114 * happens in print_cpuinfo() when we have a console 115 */ 116 ret = set_flex_ratio_to_tdp_nominal(); 117 if (ret) 118 return ret; 119 120 return 0; 121 } 122 123 #define PCH_EHCI0_TEMP_BAR0 0xe8000000 124 #define PCH_EHCI1_TEMP_BAR0 0xe8000400 125 #define PCH_XHCI_TEMP_BAR0 0xe8001000 126 127 /* 128 * Setup USB controller MMIO BAR to prevent the reference code from 129 * resetting the controller. 130 * 131 * The BAR will be re-assigned during device enumeration so these are only 132 * temporary. 133 * 134 * This is used to speed up the resume path. 135 */ 136 static void enable_usb_bar(struct udevice *bus) 137 { 138 pci_dev_t usb0 = PCH_EHCI1_DEV; 139 pci_dev_t usb1 = PCH_EHCI2_DEV; 140 pci_dev_t usb3 = PCH_XHCI_DEV; 141 ulong cmd; 142 143 /* USB Controller 1 */ 144 pci_bus_write_config(bus, usb0, PCI_BASE_ADDRESS_0, 145 PCH_EHCI0_TEMP_BAR0, PCI_SIZE_32); 146 pci_bus_read_config(bus, usb0, PCI_COMMAND, &cmd, PCI_SIZE_32); 147 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 148 pci_bus_write_config(bus, usb0, PCI_COMMAND, cmd, PCI_SIZE_32); 149 150 /* USB Controller 2 */ 151 pci_bus_write_config(bus, usb1, PCI_BASE_ADDRESS_0, 152 PCH_EHCI1_TEMP_BAR0, PCI_SIZE_32); 153 pci_bus_read_config(bus, usb1, PCI_COMMAND, &cmd, PCI_SIZE_32); 154 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 155 pci_bus_write_config(bus, usb1, PCI_COMMAND, cmd, PCI_SIZE_32); 156 157 /* USB3 Controller 1 */ 158 pci_bus_write_config(bus, usb3, PCI_BASE_ADDRESS_0, 159 PCH_XHCI_TEMP_BAR0, PCI_SIZE_32); 160 pci_bus_read_config(bus, usb3, PCI_COMMAND, &cmd, PCI_SIZE_32); 161 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 162 pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32); 163 } 164 165 static int report_bist_failure(void) 166 { 167 if (gd->arch.bist != 0) { 168 post_code(POST_BIST_FAILURE); 169 printf("BIST failed: %08x\n", gd->arch.bist); 170 return -EFAULT; 171 } 172 173 return 0; 174 } 175 176 int print_cpuinfo(void) 177 { 178 enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; 179 char processor_name[CPU_MAX_NAME_LEN]; 180 struct udevice *dev, *lpc; 181 const char *name; 182 uint32_t pm1_cnt; 183 uint16_t pm1_sts; 184 int ret; 185 186 /* Halt if there was a built in self test failure */ 187 ret = report_bist_failure(); 188 if (ret) 189 return ret; 190 191 enable_lapic(); 192 193 ret = microcode_update_intel(); 194 if (ret) 195 return ret; 196 197 /* Enable upper 128bytes of CMOS */ 198 writel(1 << 2, RCB_REG(RC)); 199 200 /* TODO: cmos_post_init() */ 201 if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) { 202 debug("soft reset detected\n"); 203 boot_mode = PEI_BOOT_SOFT_RESET; 204 205 /* System is not happy after keyboard reset... */ 206 debug("Issuing CF9 warm reset\n"); 207 reset_cpu(0); 208 } 209 210 /* Early chipset init required before RAM init can work */ 211 uclass_first_device(UCLASS_NORTHBRIDGE, &dev); 212 213 ret = uclass_first_device(UCLASS_LPC, &lpc); 214 if (ret) 215 return ret; 216 if (!dev) 217 return -ENODEV; 218 219 /* Cause the SATA device to do its early init */ 220 uclass_first_device(UCLASS_DISK, &dev); 221 222 /* Check PM1_STS[15] to see if we are waking from Sx */ 223 pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); 224 225 /* Read PM1_CNT[12:10] to determine which Sx state */ 226 pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); 227 228 if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { 229 debug("Resume from S3 detected, but disabled.\n"); 230 } else { 231 /* 232 * TODO: An indication of life might be possible here (e.g. 233 * keyboard light) 234 */ 235 } 236 post_code(POST_EARLY_INIT); 237 238 /* Enable SPD ROMs and DDR-III DRAM */ 239 ret = uclass_first_device(UCLASS_I2C, &dev); 240 if (ret) 241 return ret; 242 if (!dev) 243 return -ENODEV; 244 245 /* Prepare USB controller early in S3 resume */ 246 if (boot_mode == PEI_BOOT_RESUME) 247 enable_usb_bar(pci_get_controller(lpc->parent)); 248 249 gd->arch.pei_boot_mode = boot_mode; 250 251 /* Print processor name */ 252 name = cpu_get_name(processor_name); 253 printf("CPU: %s\n", name); 254 255 post_code(POST_CPU_INFO); 256 257 return 0; 258 } 259 260 void board_debug_uart_init(void) 261 { 262 /* This enables the debug UART */ 263 pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN, 264 PCI_SIZE_16); 265 } 266