1 /* 2 * Copyright (c) 2014 Google, Inc 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * Some portions from coreboot src/mainboard/google/link/romstage.c 7 * and src/cpu/intel/model_206ax/bootblock.c 8 * Copyright (C) 2007-2010 coresystems GmbH 9 * Copyright (C) 2011 Google Inc. 10 * 11 * SPDX-License-Identifier: GPL-2.0 12 */ 13 14 #include <common.h> 15 #include <errno.h> 16 #include <fdtdec.h> 17 #include <asm/cpu.h> 18 #include <asm/io.h> 19 #include <asm/lapic.h> 20 #include <asm/msr.h> 21 #include <asm/mtrr.h> 22 #include <asm/pci.h> 23 #include <asm/post.h> 24 #include <asm/processor.h> 25 #include <asm/arch/model_206ax.h> 26 #include <asm/arch/microcode.h> 27 #include <asm/arch/pch.h> 28 #include <asm/arch/sandybridge.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev) 33 { 34 /* Enable port 80 POST on LPC */ 35 pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); 36 clrbits_le32(RCB_REG(GCS), 4); 37 } 38 39 /* 40 * Enable Prefetching and Caching. 41 */ 42 static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev) 43 { 44 u8 reg8; 45 46 pci_hose_read_config_byte(hose, dev, 0xdc, ®8); 47 reg8 &= ~(3 << 2); 48 reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ 49 pci_hose_write_config_byte(hose, dev, 0xdc, reg8); 50 } 51 52 static int set_flex_ratio_to_tdp_nominal(void) 53 { 54 msr_t flex_ratio, msr; 55 u8 nominal_ratio; 56 57 /* Minimum CPU revision for configurable TDP support */ 58 if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) 59 return -EINVAL; 60 61 /* Check for Flex Ratio support */ 62 flex_ratio = msr_read(MSR_FLEX_RATIO); 63 if (!(flex_ratio.lo & FLEX_RATIO_EN)) 64 return -EINVAL; 65 66 /* Check for >0 configurable TDPs */ 67 msr = msr_read(MSR_PLATFORM_INFO); 68 if (((msr.hi >> 1) & 3) == 0) 69 return -EINVAL; 70 71 /* Use nominal TDP ratio for flex ratio */ 72 msr = msr_read(MSR_CONFIG_TDP_NOMINAL); 73 nominal_ratio = msr.lo & 0xff; 74 75 /* See if flex ratio is already set to nominal TDP ratio */ 76 if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) 77 return 0; 78 79 /* Set flex ratio to nominal TDP ratio */ 80 flex_ratio.lo &= ~0xff00; 81 flex_ratio.lo |= nominal_ratio << 8; 82 flex_ratio.lo |= FLEX_RATIO_LOCK; 83 msr_write(MSR_FLEX_RATIO, flex_ratio); 84 85 /* Set flex ratio in soft reset data register bits 11:6 */ 86 clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6, 87 (nominal_ratio & 0x3f) << 6); 88 89 /* Set soft reset control to use register value */ 90 setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1); 91 92 /* Issue warm reset, will be "CPU only" due to soft reset data */ 93 outb(0x0, PORT_RESET); 94 outb(0x6, PORT_RESET); 95 cpu_hlt(); 96 97 /* Not reached */ 98 return -EINVAL; 99 } 100 101 static void set_spi_speed(void) 102 { 103 u32 fdod; 104 105 /* Observe SPI Descriptor Component Section 0 */ 106 writel(0x1000, RCB_REG(SPI_DESC_COMP0)); 107 108 /* Extract the1 Write/Erase SPI Frequency from descriptor */ 109 fdod = readl(RCB_REG(SPI_FREQ_WR_ERA)); 110 fdod >>= 24; 111 fdod &= 7; 112 113 /* Set Software Sequence frequency to match */ 114 clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod); 115 } 116 117 int arch_cpu_init(void) 118 { 119 const void *blob = gd->fdt_blob; 120 struct pci_controller *hose; 121 int node; 122 int ret; 123 124 post_code(POST_CPU_INIT); 125 timer_set_base(rdtsc()); 126 127 ret = x86_cpu_init_f(); 128 if (ret) 129 return ret; 130 131 ret = pci_early_init_hose(&hose); 132 if (ret) 133 return ret; 134 135 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC); 136 if (node < 0) 137 return -ENOENT; 138 ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV); 139 if (ret) 140 return ret; 141 142 enable_spi_prefetch(hose, PCH_LPC_DEV); 143 144 /* This is already done in start.S, but let's do it in C */ 145 enable_port80_on_lpc(hose, PCH_LPC_DEV); 146 147 set_spi_speed(); 148 149 /* 150 * We should do as little as possible before the serial console is 151 * up. Perhaps this should move to later. Our next lot of init 152 * happens in print_cpuinfo() when we have a console 153 */ 154 ret = set_flex_ratio_to_tdp_nominal(); 155 if (ret) 156 return ret; 157 158 return 0; 159 } 160 161 static int enable_smbus(void) 162 { 163 pci_dev_t dev; 164 uint16_t value; 165 166 /* Set the SMBus device statically. */ 167 dev = PCI_BDF(0x0, 0x1f, 0x3); 168 169 /* Check to make sure we've got the right device. */ 170 value = pci_read_config16(dev, 0x0); 171 if (value != 0x8086) { 172 printf("SMBus controller not found\n"); 173 return -ENOSYS; 174 } 175 176 /* Set SMBus I/O base. */ 177 pci_write_config32(dev, SMB_BASE, 178 SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); 179 180 /* Set SMBus enable. */ 181 pci_write_config8(dev, HOSTC, HST_EN); 182 183 /* Set SMBus I/O space enable. */ 184 pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); 185 186 /* Disable interrupt generation. */ 187 outb(0, SMBUS_IO_BASE + SMBHSTCTL); 188 189 /* Clear any lingering errors, so transactions can run. */ 190 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); 191 debug("SMBus controller enabled\n"); 192 193 return 0; 194 } 195 196 #define PCH_EHCI0_TEMP_BAR0 0xe8000000 197 #define PCH_EHCI1_TEMP_BAR0 0xe8000400 198 #define PCH_XHCI_TEMP_BAR0 0xe8001000 199 200 /* 201 * Setup USB controller MMIO BAR to prevent the reference code from 202 * resetting the controller. 203 * 204 * The BAR will be re-assigned during device enumeration so these are only 205 * temporary. 206 * 207 * This is used to speed up the resume path. 208 */ 209 static void enable_usb_bar(void) 210 { 211 pci_dev_t usb0 = PCH_EHCI1_DEV; 212 pci_dev_t usb1 = PCH_EHCI2_DEV; 213 pci_dev_t usb3 = PCH_XHCI_DEV; 214 u32 cmd; 215 216 /* USB Controller 1 */ 217 pci_write_config32(usb0, PCI_BASE_ADDRESS_0, 218 PCH_EHCI0_TEMP_BAR0); 219 cmd = pci_read_config32(usb0, PCI_COMMAND); 220 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 221 pci_write_config32(usb0, PCI_COMMAND, cmd); 222 223 /* USB Controller 1 */ 224 pci_write_config32(usb1, PCI_BASE_ADDRESS_0, 225 PCH_EHCI1_TEMP_BAR0); 226 cmd = pci_read_config32(usb1, PCI_COMMAND); 227 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 228 pci_write_config32(usb1, PCI_COMMAND, cmd); 229 230 /* USB3 Controller */ 231 pci_write_config32(usb3, PCI_BASE_ADDRESS_0, 232 PCH_XHCI_TEMP_BAR0); 233 cmd = pci_read_config32(usb3, PCI_COMMAND); 234 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 235 pci_write_config32(usb3, PCI_COMMAND, cmd); 236 } 237 238 static int report_bist_failure(void) 239 { 240 if (gd->arch.bist != 0) { 241 post_code(POST_BIST_FAILURE); 242 printf("BIST failed: %08x\n", gd->arch.bist); 243 return -EFAULT; 244 } 245 246 return 0; 247 } 248 249 int print_cpuinfo(void) 250 { 251 enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; 252 char processor_name[CPU_MAX_NAME_LEN]; 253 const char *name; 254 uint32_t pm1_cnt; 255 uint16_t pm1_sts; 256 int ret; 257 258 /* Halt if there was a built in self test failure */ 259 ret = report_bist_failure(); 260 if (ret) 261 return ret; 262 263 enable_lapic(); 264 265 ret = microcode_update_intel(); 266 if (ret) 267 return ret; 268 269 /* Enable upper 128bytes of CMOS */ 270 writel(1 << 2, RCB_REG(RC)); 271 272 /* TODO: cmos_post_init() */ 273 if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) { 274 debug("soft reset detected\n"); 275 boot_mode = PEI_BOOT_SOFT_RESET; 276 277 /* System is not happy after keyboard reset... */ 278 debug("Issuing CF9 warm reset\n"); 279 outb(0x6, 0xcf9); 280 cpu_hlt(); 281 } 282 283 /* Early chipset init required before RAM init can work */ 284 sandybridge_early_init(SANDYBRIDGE_MOBILE); 285 286 /* Check PM1_STS[15] to see if we are waking from Sx */ 287 pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); 288 289 /* Read PM1_CNT[12:10] to determine which Sx state */ 290 pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); 291 292 if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { 293 #if CONFIG_HAVE_ACPI_RESUME 294 debug("Resume from S3 detected.\n"); 295 boot_mode = PEI_BOOT_RESUME; 296 /* Clear SLP_TYPE. This will break stage2 but 297 * we care for that when we get there. 298 */ 299 outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); 300 #else 301 debug("Resume from S3 detected, but disabled.\n"); 302 #endif 303 } else { 304 /* 305 * TODO: An indication of life might be possible here (e.g. 306 * keyboard light) 307 */ 308 } 309 post_code(POST_EARLY_INIT); 310 311 /* Enable SPD ROMs and DDR-III DRAM */ 312 ret = enable_smbus(); 313 if (ret) 314 return ret; 315 316 /* Prepare USB controller early in S3 resume */ 317 if (boot_mode == PEI_BOOT_RESUME) 318 enable_usb_bar(); 319 320 gd->arch.pei_boot_mode = boot_mode; 321 322 /* TODO: Move this to the board or driver */ 323 pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); 324 pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10); 325 326 /* Print processor name */ 327 name = cpu_get_name(processor_name); 328 printf("CPU: %s\n", name); 329 330 post_code(POST_CPU_INFO); 331 332 return 0; 333 } 334