1 /* 2 * Copyright (c) 2014 Google, Inc 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * Some portions from coreboot src/mainboard/google/link/romstage.c 7 * and src/cpu/intel/model_206ax/bootblock.c 8 * Copyright (C) 2007-2010 coresystems GmbH 9 * Copyright (C) 2011 Google Inc. 10 * 11 * SPDX-License-Identifier: GPL-2.0 12 */ 13 14 #include <common.h> 15 #include <errno.h> 16 #include <fdtdec.h> 17 #include <asm/cpu.h> 18 #include <asm/io.h> 19 #include <asm/lapic.h> 20 #include <asm/msr.h> 21 #include <asm/mtrr.h> 22 #include <asm/pci.h> 23 #include <asm/post.h> 24 #include <asm/processor.h> 25 #include <asm/arch/model_206ax.h> 26 #include <asm/arch/microcode.h> 27 #include <asm/arch/pch.h> 28 #include <asm/arch/sandybridge.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev) 33 { 34 /* Enable port 80 POST on LPC */ 35 pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); 36 clrbits_le32(RCB_REG(GCS), 4); 37 } 38 39 /* 40 * Enable Prefetching and Caching. 41 */ 42 static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev) 43 { 44 u8 reg8; 45 46 pci_hose_read_config_byte(hose, dev, 0xdc, ®8); 47 reg8 &= ~(3 << 2); 48 reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ 49 pci_hose_write_config_byte(hose, dev, 0xdc, reg8); 50 } 51 52 static void set_var_mtrr( 53 unsigned reg, unsigned base, unsigned size, unsigned type) 54 55 { 56 /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ 57 /* FIXME: It only support 4G less range */ 58 wrmsr(MTRRphysBase_MSR(reg), base | type, 0); 59 wrmsr(MTRRphysMask_MSR(reg), ~(size - 1) | MTRRphysMaskValid, 60 (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1); 61 } 62 63 static void enable_rom_caching(void) 64 { 65 disable_caches(); 66 set_var_mtrr(1, 0xffc00000, 4 << 20, MTRR_TYPE_WRPROT); 67 enable_caches(); 68 69 /* Enable Variable MTRRs */ 70 wrmsr(MTRRdefType_MSR, 0x800, 0); 71 } 72 73 static int set_flex_ratio_to_tdp_nominal(void) 74 { 75 msr_t flex_ratio, msr; 76 u8 nominal_ratio; 77 78 /* Minimum CPU revision for configurable TDP support */ 79 if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) 80 return -EINVAL; 81 82 /* Check for Flex Ratio support */ 83 flex_ratio = msr_read(MSR_FLEX_RATIO); 84 if (!(flex_ratio.lo & FLEX_RATIO_EN)) 85 return -EINVAL; 86 87 /* Check for >0 configurable TDPs */ 88 msr = msr_read(MSR_PLATFORM_INFO); 89 if (((msr.hi >> 1) & 3) == 0) 90 return -EINVAL; 91 92 /* Use nominal TDP ratio for flex ratio */ 93 msr = msr_read(MSR_CONFIG_TDP_NOMINAL); 94 nominal_ratio = msr.lo & 0xff; 95 96 /* See if flex ratio is already set to nominal TDP ratio */ 97 if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) 98 return 0; 99 100 /* Set flex ratio to nominal TDP ratio */ 101 flex_ratio.lo &= ~0xff00; 102 flex_ratio.lo |= nominal_ratio << 8; 103 flex_ratio.lo |= FLEX_RATIO_LOCK; 104 msr_write(MSR_FLEX_RATIO, flex_ratio); 105 106 /* Set flex ratio in soft reset data register bits 11:6 */ 107 clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6, 108 (nominal_ratio & 0x3f) << 6); 109 110 /* Set soft reset control to use register value */ 111 setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1); 112 113 /* Issue warm reset, will be "CPU only" due to soft reset data */ 114 outb(0x0, PORT_RESET); 115 outb(0x6, PORT_RESET); 116 cpu_hlt(); 117 118 /* Not reached */ 119 return -EINVAL; 120 } 121 122 static void set_spi_speed(void) 123 { 124 u32 fdod; 125 126 /* Observe SPI Descriptor Component Section 0 */ 127 writel(0x1000, RCB_REG(SPI_DESC_COMP0)); 128 129 /* Extract the1 Write/Erase SPI Frequency from descriptor */ 130 fdod = readl(RCB_REG(SPI_FREQ_WR_ERA)); 131 fdod >>= 24; 132 fdod &= 7; 133 134 /* Set Software Sequence frequency to match */ 135 clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod); 136 } 137 138 int arch_cpu_init(void) 139 { 140 const void *blob = gd->fdt_blob; 141 struct pci_controller *hose; 142 int node; 143 int ret; 144 145 post_code(POST_CPU_INIT); 146 timer_set_base(rdtsc()); 147 148 ret = x86_cpu_init_f(); 149 if (ret) 150 return ret; 151 152 ret = pci_early_init_hose(&hose); 153 if (ret) 154 return ret; 155 156 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC); 157 if (node < 0) 158 return -ENOENT; 159 ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV); 160 if (ret) 161 return ret; 162 163 enable_spi_prefetch(hose, PCH_LPC_DEV); 164 165 /* This is already done in start.S, but let's do it in C */ 166 enable_port80_on_lpc(hose, PCH_LPC_DEV); 167 168 /* already done in car.S */ 169 if (false) 170 enable_rom_caching(); 171 172 set_spi_speed(); 173 174 /* 175 * We should do as little as possible before the serial console is 176 * up. Perhaps this should move to later. Our next lot of init 177 * happens in print_cpuinfo() when we have a console 178 */ 179 ret = set_flex_ratio_to_tdp_nominal(); 180 if (ret) 181 return ret; 182 183 return 0; 184 } 185 186 static int enable_smbus(void) 187 { 188 pci_dev_t dev; 189 uint16_t value; 190 191 /* Set the SMBus device statically. */ 192 dev = PCI_BDF(0x0, 0x1f, 0x3); 193 194 /* Check to make sure we've got the right device. */ 195 value = pci_read_config16(dev, 0x0); 196 if (value != 0x8086) { 197 printf("SMBus controller not found\n"); 198 return -ENOSYS; 199 } 200 201 /* Set SMBus I/O base. */ 202 pci_write_config32(dev, SMB_BASE, 203 SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); 204 205 /* Set SMBus enable. */ 206 pci_write_config8(dev, HOSTC, HST_EN); 207 208 /* Set SMBus I/O space enable. */ 209 pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); 210 211 /* Disable interrupt generation. */ 212 outb(0, SMBUS_IO_BASE + SMBHSTCTL); 213 214 /* Clear any lingering errors, so transactions can run. */ 215 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); 216 debug("SMBus controller enabled\n"); 217 218 return 0; 219 } 220 221 #define PCH_EHCI0_TEMP_BAR0 0xe8000000 222 #define PCH_EHCI1_TEMP_BAR0 0xe8000400 223 #define PCH_XHCI_TEMP_BAR0 0xe8001000 224 225 /* 226 * Setup USB controller MMIO BAR to prevent the reference code from 227 * resetting the controller. 228 * 229 * The BAR will be re-assigned during device enumeration so these are only 230 * temporary. 231 * 232 * This is used to speed up the resume path. 233 */ 234 static void enable_usb_bar(void) 235 { 236 pci_dev_t usb0 = PCH_EHCI1_DEV; 237 pci_dev_t usb1 = PCH_EHCI2_DEV; 238 pci_dev_t usb3 = PCH_XHCI_DEV; 239 u32 cmd; 240 241 /* USB Controller 1 */ 242 pci_write_config32(usb0, PCI_BASE_ADDRESS_0, 243 PCH_EHCI0_TEMP_BAR0); 244 cmd = pci_read_config32(usb0, PCI_COMMAND); 245 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 246 pci_write_config32(usb0, PCI_COMMAND, cmd); 247 248 /* USB Controller 1 */ 249 pci_write_config32(usb1, PCI_BASE_ADDRESS_0, 250 PCH_EHCI1_TEMP_BAR0); 251 cmd = pci_read_config32(usb1, PCI_COMMAND); 252 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 253 pci_write_config32(usb1, PCI_COMMAND, cmd); 254 255 /* USB3 Controller */ 256 pci_write_config32(usb3, PCI_BASE_ADDRESS_0, 257 PCH_XHCI_TEMP_BAR0); 258 cmd = pci_read_config32(usb3, PCI_COMMAND); 259 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 260 pci_write_config32(usb3, PCI_COMMAND, cmd); 261 } 262 263 static int report_bist_failure(void) 264 { 265 if (gd->arch.bist != 0) { 266 post_code(POST_BIST_FAILURE); 267 printf("BIST failed: %08x\n", gd->arch.bist); 268 return -EFAULT; 269 } 270 271 return 0; 272 } 273 274 int print_cpuinfo(void) 275 { 276 enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; 277 char processor_name[CPU_MAX_NAME_LEN]; 278 const char *name; 279 uint32_t pm1_cnt; 280 uint16_t pm1_sts; 281 int ret; 282 283 /* Halt if there was a built in self test failure */ 284 ret = report_bist_failure(); 285 if (ret) 286 return ret; 287 288 enable_lapic(); 289 290 ret = microcode_update_intel(); 291 if (ret && ret != -ENOENT && ret != -EEXIST) 292 return ret; 293 294 /* Enable upper 128bytes of CMOS */ 295 writel(1 << 2, RCB_REG(RC)); 296 297 /* TODO: cmos_post_init() */ 298 if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) { 299 debug("soft reset detected\n"); 300 boot_mode = PEI_BOOT_SOFT_RESET; 301 302 /* System is not happy after keyboard reset... */ 303 debug("Issuing CF9 warm reset\n"); 304 outb(0x6, 0xcf9); 305 cpu_hlt(); 306 } 307 308 /* Early chipset init required before RAM init can work */ 309 sandybridge_early_init(SANDYBRIDGE_MOBILE); 310 311 /* Check PM1_STS[15] to see if we are waking from Sx */ 312 pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); 313 314 /* Read PM1_CNT[12:10] to determine which Sx state */ 315 pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); 316 317 if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { 318 #if CONFIG_HAVE_ACPI_RESUME 319 debug("Resume from S3 detected.\n"); 320 boot_mode = PEI_BOOT_RESUME; 321 /* Clear SLP_TYPE. This will break stage2 but 322 * we care for that when we get there. 323 */ 324 outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); 325 #else 326 debug("Resume from S3 detected, but disabled.\n"); 327 #endif 328 } else { 329 /* 330 * TODO: An indication of life might be possible here (e.g. 331 * keyboard light) 332 */ 333 } 334 post_code(POST_EARLY_INIT); 335 336 /* Enable SPD ROMs and DDR-III DRAM */ 337 ret = enable_smbus(); 338 if (ret) 339 return ret; 340 341 /* Prepare USB controller early in S3 resume */ 342 if (boot_mode == PEI_BOOT_RESUME) 343 enable_usb_bar(); 344 345 gd->arch.pei_boot_mode = boot_mode; 346 347 /* TODO: Move this to the board or driver */ 348 pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); 349 pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10); 350 351 /* Print processor name */ 352 name = cpu_get_name(processor_name); 353 printf("CPU: %s\n", name); 354 355 post_code(POST_CPU_INFO); 356 357 return 0; 358 } 359