1 /* 2 * Copyright (c) 2014 Google, Inc 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * Some portions from coreboot src/mainboard/google/link/romstage.c 7 * and src/cpu/intel/model_206ax/bootblock.c 8 * Copyright (C) 2007-2010 coresystems GmbH 9 * Copyright (C) 2011 Google Inc. 10 * 11 * SPDX-License-Identifier: GPL-2.0 12 */ 13 14 #include <common.h> 15 #include <dm.h> 16 #include <errno.h> 17 #include <fdtdec.h> 18 #include <pch.h> 19 #include <asm/cpu.h> 20 #include <asm/io.h> 21 #include <asm/lapic.h> 22 #include <asm/msr.h> 23 #include <asm/mtrr.h> 24 #include <asm/pci.h> 25 #include <asm/post.h> 26 #include <asm/processor.h> 27 #include <asm/arch/model_206ax.h> 28 #include <asm/arch/microcode.h> 29 #include <asm/arch/pch.h> 30 #include <asm/arch/sandybridge.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 static int set_flex_ratio_to_tdp_nominal(void) 35 { 36 msr_t flex_ratio, msr; 37 u8 nominal_ratio; 38 39 /* Minimum CPU revision for configurable TDP support */ 40 if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) 41 return -EINVAL; 42 43 /* Check for Flex Ratio support */ 44 flex_ratio = msr_read(MSR_FLEX_RATIO); 45 if (!(flex_ratio.lo & FLEX_RATIO_EN)) 46 return -EINVAL; 47 48 /* Check for >0 configurable TDPs */ 49 msr = msr_read(MSR_PLATFORM_INFO); 50 if (((msr.hi >> 1) & 3) == 0) 51 return -EINVAL; 52 53 /* Use nominal TDP ratio for flex ratio */ 54 msr = msr_read(MSR_CONFIG_TDP_NOMINAL); 55 nominal_ratio = msr.lo & 0xff; 56 57 /* See if flex ratio is already set to nominal TDP ratio */ 58 if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) 59 return 0; 60 61 /* Set flex ratio to nominal TDP ratio */ 62 flex_ratio.lo &= ~0xff00; 63 flex_ratio.lo |= nominal_ratio << 8; 64 flex_ratio.lo |= FLEX_RATIO_LOCK; 65 msr_write(MSR_FLEX_RATIO, flex_ratio); 66 67 /* Set flex ratio in soft reset data register bits 11:6 */ 68 clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6, 69 (nominal_ratio & 0x3f) << 6); 70 71 /* Set soft reset control to use register value */ 72 setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1); 73 74 /* Issue warm reset, will be "CPU only" due to soft reset data */ 75 outb(0x0, PORT_RESET); 76 outb(SYS_RST | RST_CPU, PORT_RESET); 77 cpu_hlt(); 78 79 /* Not reached */ 80 return -EINVAL; 81 } 82 83 int arch_cpu_init(void) 84 { 85 post_code(POST_CPU_INIT); 86 87 return x86_cpu_init_f(); 88 } 89 90 int arch_cpu_init_dm(void) 91 { 92 struct pci_controller *hose; 93 struct udevice *bus, *dev; 94 int ret; 95 96 post_code(0x70); 97 ret = uclass_get_device(UCLASS_PCI, 0, &bus); 98 post_code(0x71); 99 if (ret) 100 return ret; 101 post_code(0x72); 102 hose = dev_get_uclass_priv(bus); 103 104 /* TODO(sjg@chromium.org): Get rid of gd->hose */ 105 gd->hose = hose; 106 107 ret = uclass_first_device(UCLASS_LPC, &dev); 108 if (!dev) 109 return -ENODEV; 110 111 /* 112 * We should do as little as possible before the serial console is 113 * up. Perhaps this should move to later. Our next lot of init 114 * happens in print_cpuinfo() when we have a console 115 */ 116 ret = set_flex_ratio_to_tdp_nominal(); 117 if (ret) 118 return ret; 119 120 return 0; 121 } 122 123 static int enable_smbus(void) 124 { 125 pci_dev_t dev; 126 uint16_t value; 127 128 /* Set the SMBus device statically. */ 129 dev = PCI_BDF(0x0, 0x1f, 0x3); 130 131 /* Check to make sure we've got the right device. */ 132 value = x86_pci_read_config16(dev, 0x0); 133 if (value != 0x8086) { 134 printf("SMBus controller not found\n"); 135 return -ENOSYS; 136 } 137 138 /* Set SMBus I/O base. */ 139 x86_pci_write_config32(dev, SMB_BASE, 140 SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); 141 142 /* Set SMBus enable. */ 143 x86_pci_write_config8(dev, HOSTC, HST_EN); 144 145 /* Set SMBus I/O space enable. */ 146 x86_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); 147 148 /* Disable interrupt generation. */ 149 outb(0, SMBUS_IO_BASE + SMBHSTCTL); 150 151 /* Clear any lingering errors, so transactions can run. */ 152 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); 153 debug("SMBus controller enabled\n"); 154 155 return 0; 156 } 157 158 #define PCH_EHCI0_TEMP_BAR0 0xe8000000 159 #define PCH_EHCI1_TEMP_BAR0 0xe8000400 160 #define PCH_XHCI_TEMP_BAR0 0xe8001000 161 162 /* 163 * Setup USB controller MMIO BAR to prevent the reference code from 164 * resetting the controller. 165 * 166 * The BAR will be re-assigned during device enumeration so these are only 167 * temporary. 168 * 169 * This is used to speed up the resume path. 170 */ 171 static void enable_usb_bar(void) 172 { 173 pci_dev_t usb0 = PCH_EHCI1_DEV; 174 pci_dev_t usb1 = PCH_EHCI2_DEV; 175 pci_dev_t usb3 = PCH_XHCI_DEV; 176 u32 cmd; 177 178 /* USB Controller 1 */ 179 x86_pci_write_config32(usb0, PCI_BASE_ADDRESS_0, 180 PCH_EHCI0_TEMP_BAR0); 181 cmd = x86_pci_read_config32(usb0, PCI_COMMAND); 182 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 183 x86_pci_write_config32(usb0, PCI_COMMAND, cmd); 184 185 /* USB Controller 1 */ 186 x86_pci_write_config32(usb1, PCI_BASE_ADDRESS_0, 187 PCH_EHCI1_TEMP_BAR0); 188 cmd = x86_pci_read_config32(usb1, PCI_COMMAND); 189 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 190 x86_pci_write_config32(usb1, PCI_COMMAND, cmd); 191 192 /* USB3 Controller */ 193 x86_pci_write_config32(usb3, PCI_BASE_ADDRESS_0, 194 PCH_XHCI_TEMP_BAR0); 195 cmd = x86_pci_read_config32(usb3, PCI_COMMAND); 196 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 197 x86_pci_write_config32(usb3, PCI_COMMAND, cmd); 198 } 199 200 static int report_bist_failure(void) 201 { 202 if (gd->arch.bist != 0) { 203 post_code(POST_BIST_FAILURE); 204 printf("BIST failed: %08x\n", gd->arch.bist); 205 return -EFAULT; 206 } 207 208 return 0; 209 } 210 211 int print_cpuinfo(void) 212 { 213 enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; 214 char processor_name[CPU_MAX_NAME_LEN]; 215 struct udevice *dev, *lpc; 216 const char *name; 217 uint32_t pm1_cnt; 218 uint16_t pm1_sts; 219 int ret; 220 221 /* Halt if there was a built in self test failure */ 222 ret = report_bist_failure(); 223 if (ret) 224 return ret; 225 226 enable_lapic(); 227 228 ret = microcode_update_intel(); 229 if (ret) 230 return ret; 231 232 /* Enable upper 128bytes of CMOS */ 233 writel(1 << 2, RCB_REG(RC)); 234 235 /* TODO: cmos_post_init() */ 236 if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) { 237 debug("soft reset detected\n"); 238 boot_mode = PEI_BOOT_SOFT_RESET; 239 240 /* System is not happy after keyboard reset... */ 241 debug("Issuing CF9 warm reset\n"); 242 reset_cpu(0); 243 } 244 245 /* Early chipset init required before RAM init can work */ 246 uclass_first_device(UCLASS_NORTHBRIDGE, &dev); 247 248 ret = uclass_first_device(UCLASS_LPC, &lpc); 249 if (ret) 250 return ret; 251 if (!dev) 252 return -ENODEV; 253 254 /* Check PM1_STS[15] to see if we are waking from Sx */ 255 pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); 256 257 /* Read PM1_CNT[12:10] to determine which Sx state */ 258 pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); 259 260 if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { 261 debug("Resume from S3 detected, but disabled.\n"); 262 } else { 263 /* 264 * TODO: An indication of life might be possible here (e.g. 265 * keyboard light) 266 */ 267 } 268 post_code(POST_EARLY_INIT); 269 270 /* Enable SPD ROMs and DDR-III DRAM */ 271 ret = enable_smbus(); 272 if (ret) 273 return ret; 274 275 /* Prepare USB controller early in S3 resume */ 276 if (boot_mode == PEI_BOOT_RESUME) 277 enable_usb_bar(); 278 279 gd->arch.pei_boot_mode = boot_mode; 280 281 /* Print processor name */ 282 name = cpu_get_name(processor_name); 283 printf("CPU: %s\n", name); 284 285 post_code(POST_CPU_INFO); 286 287 return 0; 288 } 289 290 void board_debug_uart_init(void) 291 { 292 /* This enables the debug UART */ 293 pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN, 294 PCI_SIZE_16); 295 } 296