1 /* 2 * Copyright (c) 2014 Google, Inc 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * Some portions from coreboot src/mainboard/google/link/romstage.c 7 * and src/cpu/intel/model_206ax/bootblock.c 8 * Copyright (C) 2007-2010 coresystems GmbH 9 * Copyright (C) 2011 Google Inc. 10 * 11 * SPDX-License-Identifier: GPL-2.0 12 */ 13 14 #include <common.h> 15 #include <dm.h> 16 #include <errno.h> 17 #include <fdtdec.h> 18 #include <asm/cpu.h> 19 #include <asm/io.h> 20 #include <asm/lapic.h> 21 #include <asm/msr.h> 22 #include <asm/mtrr.h> 23 #include <asm/pci.h> 24 #include <asm/post.h> 25 #include <asm/processor.h> 26 #include <asm/arch/model_206ax.h> 27 #include <asm/arch/microcode.h> 28 #include <asm/arch/pch.h> 29 #include <asm/arch/sandybridge.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev) 34 { 35 /* Enable port 80 POST on LPC */ 36 pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); 37 clrbits_le32(RCB_REG(GCS), 4); 38 } 39 40 /* 41 * Enable Prefetching and Caching. 42 */ 43 static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev) 44 { 45 u8 reg8; 46 47 pci_hose_read_config_byte(hose, dev, 0xdc, ®8); 48 reg8 &= ~(3 << 2); 49 reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ 50 pci_hose_write_config_byte(hose, dev, 0xdc, reg8); 51 } 52 53 static int set_flex_ratio_to_tdp_nominal(void) 54 { 55 msr_t flex_ratio, msr; 56 u8 nominal_ratio; 57 58 /* Minimum CPU revision for configurable TDP support */ 59 if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) 60 return -EINVAL; 61 62 /* Check for Flex Ratio support */ 63 flex_ratio = msr_read(MSR_FLEX_RATIO); 64 if (!(flex_ratio.lo & FLEX_RATIO_EN)) 65 return -EINVAL; 66 67 /* Check for >0 configurable TDPs */ 68 msr = msr_read(MSR_PLATFORM_INFO); 69 if (((msr.hi >> 1) & 3) == 0) 70 return -EINVAL; 71 72 /* Use nominal TDP ratio for flex ratio */ 73 msr = msr_read(MSR_CONFIG_TDP_NOMINAL); 74 nominal_ratio = msr.lo & 0xff; 75 76 /* See if flex ratio is already set to nominal TDP ratio */ 77 if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) 78 return 0; 79 80 /* Set flex ratio to nominal TDP ratio */ 81 flex_ratio.lo &= ~0xff00; 82 flex_ratio.lo |= nominal_ratio << 8; 83 flex_ratio.lo |= FLEX_RATIO_LOCK; 84 msr_write(MSR_FLEX_RATIO, flex_ratio); 85 86 /* Set flex ratio in soft reset data register bits 11:6 */ 87 clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6, 88 (nominal_ratio & 0x3f) << 6); 89 90 /* Set soft reset control to use register value */ 91 setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1); 92 93 /* Issue warm reset, will be "CPU only" due to soft reset data */ 94 outb(0x0, PORT_RESET); 95 outb(SYS_RST | RST_CPU, PORT_RESET); 96 cpu_hlt(); 97 98 /* Not reached */ 99 return -EINVAL; 100 } 101 102 static void set_spi_speed(void) 103 { 104 u32 fdod; 105 106 /* Observe SPI Descriptor Component Section 0 */ 107 writel(0x1000, RCB_REG(SPI_DESC_COMP0)); 108 109 /* Extract the1 Write/Erase SPI Frequency from descriptor */ 110 fdod = readl(RCB_REG(SPI_FREQ_WR_ERA)); 111 fdod >>= 24; 112 fdod &= 7; 113 114 /* Set Software Sequence frequency to match */ 115 clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod); 116 } 117 118 int arch_cpu_init(void) 119 { 120 post_code(POST_CPU_INIT); 121 122 return x86_cpu_init_f(); 123 } 124 125 int arch_cpu_init_dm(void) 126 { 127 const void *blob = gd->fdt_blob; 128 struct pci_controller *hose; 129 struct udevice *bus; 130 int node; 131 int ret; 132 133 post_code(0x70); 134 ret = uclass_get_device(UCLASS_PCI, 0, &bus); 135 post_code(0x71); 136 if (ret) 137 return ret; 138 post_code(0x72); 139 hose = dev_get_uclass_priv(bus); 140 141 /* TODO(sjg@chromium.org): Get rid of gd->hose */ 142 gd->hose = hose; 143 144 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); 145 if (node < 0) 146 return -ENOENT; 147 ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV); 148 if (ret) 149 return ret; 150 151 enable_spi_prefetch(hose, PCH_LPC_DEV); 152 153 /* This is already done in start.S, but let's do it in C */ 154 enable_port80_on_lpc(hose, PCH_LPC_DEV); 155 156 set_spi_speed(); 157 158 /* 159 * We should do as little as possible before the serial console is 160 * up. Perhaps this should move to later. Our next lot of init 161 * happens in print_cpuinfo() when we have a console 162 */ 163 ret = set_flex_ratio_to_tdp_nominal(); 164 if (ret) 165 return ret; 166 167 return 0; 168 } 169 170 static int enable_smbus(void) 171 { 172 pci_dev_t dev; 173 uint16_t value; 174 175 /* Set the SMBus device statically. */ 176 dev = PCI_BDF(0x0, 0x1f, 0x3); 177 178 /* Check to make sure we've got the right device. */ 179 value = x86_pci_read_config16(dev, 0x0); 180 if (value != 0x8086) { 181 printf("SMBus controller not found\n"); 182 return -ENOSYS; 183 } 184 185 /* Set SMBus I/O base. */ 186 x86_pci_write_config32(dev, SMB_BASE, 187 SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); 188 189 /* Set SMBus enable. */ 190 x86_pci_write_config8(dev, HOSTC, HST_EN); 191 192 /* Set SMBus I/O space enable. */ 193 x86_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); 194 195 /* Disable interrupt generation. */ 196 outb(0, SMBUS_IO_BASE + SMBHSTCTL); 197 198 /* Clear any lingering errors, so transactions can run. */ 199 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); 200 debug("SMBus controller enabled\n"); 201 202 return 0; 203 } 204 205 #define PCH_EHCI0_TEMP_BAR0 0xe8000000 206 #define PCH_EHCI1_TEMP_BAR0 0xe8000400 207 #define PCH_XHCI_TEMP_BAR0 0xe8001000 208 209 /* 210 * Setup USB controller MMIO BAR to prevent the reference code from 211 * resetting the controller. 212 * 213 * The BAR will be re-assigned during device enumeration so these are only 214 * temporary. 215 * 216 * This is used to speed up the resume path. 217 */ 218 static void enable_usb_bar(void) 219 { 220 pci_dev_t usb0 = PCH_EHCI1_DEV; 221 pci_dev_t usb1 = PCH_EHCI2_DEV; 222 pci_dev_t usb3 = PCH_XHCI_DEV; 223 u32 cmd; 224 225 /* USB Controller 1 */ 226 x86_pci_write_config32(usb0, PCI_BASE_ADDRESS_0, 227 PCH_EHCI0_TEMP_BAR0); 228 cmd = x86_pci_read_config32(usb0, PCI_COMMAND); 229 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 230 x86_pci_write_config32(usb0, PCI_COMMAND, cmd); 231 232 /* USB Controller 1 */ 233 x86_pci_write_config32(usb1, PCI_BASE_ADDRESS_0, 234 PCH_EHCI1_TEMP_BAR0); 235 cmd = x86_pci_read_config32(usb1, PCI_COMMAND); 236 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 237 x86_pci_write_config32(usb1, PCI_COMMAND, cmd); 238 239 /* USB3 Controller */ 240 x86_pci_write_config32(usb3, PCI_BASE_ADDRESS_0, 241 PCH_XHCI_TEMP_BAR0); 242 cmd = x86_pci_read_config32(usb3, PCI_COMMAND); 243 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 244 x86_pci_write_config32(usb3, PCI_COMMAND, cmd); 245 } 246 247 static int report_bist_failure(void) 248 { 249 if (gd->arch.bist != 0) { 250 post_code(POST_BIST_FAILURE); 251 printf("BIST failed: %08x\n", gd->arch.bist); 252 return -EFAULT; 253 } 254 255 return 0; 256 } 257 258 int print_cpuinfo(void) 259 { 260 enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; 261 char processor_name[CPU_MAX_NAME_LEN]; 262 const char *name; 263 uint32_t pm1_cnt; 264 uint16_t pm1_sts; 265 int ret; 266 267 /* Halt if there was a built in self test failure */ 268 ret = report_bist_failure(); 269 if (ret) 270 return ret; 271 272 enable_lapic(); 273 274 ret = microcode_update_intel(); 275 if (ret) 276 return ret; 277 278 /* Enable upper 128bytes of CMOS */ 279 writel(1 << 2, RCB_REG(RC)); 280 281 /* TODO: cmos_post_init() */ 282 if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) { 283 debug("soft reset detected\n"); 284 boot_mode = PEI_BOOT_SOFT_RESET; 285 286 /* System is not happy after keyboard reset... */ 287 debug("Issuing CF9 warm reset\n"); 288 reset_cpu(0); 289 } 290 291 /* Early chipset init required before RAM init can work */ 292 sandybridge_early_init(SANDYBRIDGE_MOBILE); 293 294 /* Check PM1_STS[15] to see if we are waking from Sx */ 295 pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); 296 297 /* Read PM1_CNT[12:10] to determine which Sx state */ 298 pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); 299 300 if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { 301 debug("Resume from S3 detected, but disabled.\n"); 302 } else { 303 /* 304 * TODO: An indication of life might be possible here (e.g. 305 * keyboard light) 306 */ 307 } 308 post_code(POST_EARLY_INIT); 309 310 /* Enable SPD ROMs and DDR-III DRAM */ 311 ret = enable_smbus(); 312 if (ret) 313 return ret; 314 315 /* Prepare USB controller early in S3 resume */ 316 if (boot_mode == PEI_BOOT_RESUME) 317 enable_usb_bar(); 318 319 gd->arch.pei_boot_mode = boot_mode; 320 321 /* TODO: Move this to the board or driver */ 322 x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); 323 x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10); 324 325 /* Print processor name */ 326 name = cpu_get_name(processor_name); 327 printf("CPU: %s\n", name); 328 329 post_code(POST_CPU_INFO); 330 331 return 0; 332 } 333 334 void board_debug_uart_init(void) 335 { 336 /* This enables the debug UART */ 337 pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN, 338 PCI_SIZE_16); 339 } 340