1 /* 2 * Copyright (C) 2014 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <errno.h> 9 #include <fdtdec.h> 10 #include <malloc.h> 11 #include <asm/lapic.h> 12 #include <asm/pci.h> 13 #include <asm/arch/bd82x6x.h> 14 #include <asm/arch/model_206ax.h> 15 #include <asm/arch/pch.h> 16 #include <asm/arch/sandybridge.h> 17 18 void bd82x6x_pci_init(pci_dev_t dev) 19 { 20 u16 reg16; 21 u8 reg8; 22 23 debug("bd82x6x PCI init.\n"); 24 /* Enable Bus Master */ 25 reg16 = pci_read_config16(dev, PCI_COMMAND); 26 reg16 |= PCI_COMMAND_MASTER; 27 pci_write_config16(dev, PCI_COMMAND, reg16); 28 29 /* This device has no interrupt */ 30 pci_write_config8(dev, INTR, 0xff); 31 32 /* disable parity error response and SERR */ 33 reg16 = pci_read_config16(dev, BCTRL); 34 reg16 &= ~(1 << 0); 35 reg16 &= ~(1 << 1); 36 pci_write_config16(dev, BCTRL, reg16); 37 38 /* Master Latency Count must be set to 0x04! */ 39 reg8 = pci_read_config8(dev, SMLT); 40 reg8 &= 0x07; 41 reg8 |= (0x04 << 3); 42 pci_write_config8(dev, SMLT, reg8); 43 44 /* Will this improve throughput of bus masters? */ 45 pci_write_config8(dev, PCI_MIN_GNT, 0x06); 46 47 /* Clear errors in status registers */ 48 reg16 = pci_read_config16(dev, PSTS); 49 /* reg16 |= 0xf900; */ 50 pci_write_config16(dev, PSTS, reg16); 51 52 reg16 = pci_read_config16(dev, SECSTS); 53 /* reg16 |= 0xf900; */ 54 pci_write_config16(dev, SECSTS, reg16); 55 } 56 57 #define PCI_BRIDGE_UPDATE_COMMAND 58 void bd82x6x_pci_dev_enable_resources(pci_dev_t dev) 59 { 60 uint16_t command; 61 62 command = pci_read_config16(dev, PCI_COMMAND); 63 command |= PCI_COMMAND_IO; 64 #ifdef PCI_BRIDGE_UPDATE_COMMAND 65 /* 66 * If we write to PCI_COMMAND, on some systems this will cause the 67 * ROM and APICs to become invisible. 68 */ 69 debug("%x cmd <- %02x\n", dev, command); 70 pci_write_config16(dev, PCI_COMMAND, command); 71 #else 72 printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); 73 #endif 74 } 75 76 void bd82x6x_pci_bus_enable_resources(pci_dev_t dev) 77 { 78 uint16_t ctrl; 79 80 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); 81 ctrl |= PCI_COMMAND_IO; 82 ctrl |= PCI_BRIDGE_CTL_VGA; 83 debug("%x bridge ctrl <- %04x\n", dev, ctrl); 84 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); 85 86 bd82x6x_pci_dev_enable_resources(dev); 87 } 88 89 int bd82x6x_init_pci_devices(void) 90 { 91 const void *blob = gd->fdt_blob; 92 struct pci_controller *hose; 93 struct x86_cpu_priv *cpu; 94 int sata_node, gma_node; 95 int ret; 96 97 hose = pci_bus_to_hose(0); 98 lpc_enable(PCH_LPC_DEV); 99 lpc_init(hose, PCH_LPC_DEV); 100 sata_node = fdtdec_next_compatible(blob, 0, 101 COMPAT_INTEL_PANTHERPOINT_AHCI); 102 if (sata_node < 0) { 103 debug("%s: Cannot find SATA node\n", __func__); 104 return -EINVAL; 105 } 106 bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node); 107 bd82x6x_usb_ehci_init(PCH_EHCI1_DEV); 108 bd82x6x_usb_ehci_init(PCH_EHCI2_DEV); 109 110 cpu = calloc(1, sizeof(*cpu)); 111 if (!cpu) 112 return -ENOMEM; 113 model_206ax_init(cpu); 114 115 gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA); 116 if (gma_node < 0) { 117 debug("%s: Cannot find GMA node\n", __func__); 118 return -EINVAL; 119 } 120 ret = gma_func0_init(PCH_VIDEO_DEV, pci_bus_to_hose(0), blob, 121 gma_node); 122 if (ret) 123 return ret; 124 125 return 0; 126 } 127 128 int bd82x6x_init(void) 129 { 130 const void *blob = gd->fdt_blob; 131 int sata_node; 132 133 sata_node = fdtdec_next_compatible(blob, 0, 134 COMPAT_INTEL_PANTHERPOINT_AHCI); 135 if (sata_node < 0) { 136 debug("%s: Cannot find SATA node\n", __func__); 137 return -EINVAL; 138 } 139 140 bd82x6x_pci_init(PCH_DEV); 141 bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node); 142 northbridge_enable(PCH_DEV); 143 northbridge_init(PCH_DEV); 144 145 return 0; 146 } 147