xref: /openbmc/u-boot/arch/x86/cpu/ivybridge/bd82x6x.c (revision ed09a554)
1 /*
2  * Copyright (C) 2014 Google, Inc
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <fdtdec.h>
11 #include <malloc.h>
12 #include <asm/lapic.h>
13 #include <asm/pci.h>
14 #include <asm/arch/bd82x6x.h>
15 #include <asm/arch/model_206ax.h>
16 #include <asm/arch/pch.h>
17 #include <asm/arch/sandybridge.h>
18 
19 void bd82x6x_pci_init(pci_dev_t dev)
20 {
21 	u16 reg16;
22 	u8 reg8;
23 
24 	debug("bd82x6x PCI init.\n");
25 	/* Enable Bus Master */
26 	reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
27 	reg16 |= PCI_COMMAND_MASTER;
28 	x86_pci_write_config16(dev, PCI_COMMAND, reg16);
29 
30 	/* This device has no interrupt */
31 	x86_pci_write_config8(dev, INTR, 0xff);
32 
33 	/* disable parity error response and SERR */
34 	reg16 = x86_pci_read_config16(dev, BCTRL);
35 	reg16 &= ~(1 << 0);
36 	reg16 &= ~(1 << 1);
37 	x86_pci_write_config16(dev, BCTRL, reg16);
38 
39 	/* Master Latency Count must be set to 0x04! */
40 	reg8 = x86_pci_read_config8(dev, SMLT);
41 	reg8 &= 0x07;
42 	reg8 |= (0x04 << 3);
43 	x86_pci_write_config8(dev, SMLT, reg8);
44 
45 	/* Will this improve throughput of bus masters? */
46 	x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06);
47 
48 	/* Clear errors in status registers */
49 	reg16 = x86_pci_read_config16(dev, PSTS);
50 	/* reg16 |= 0xf900; */
51 	x86_pci_write_config16(dev, PSTS, reg16);
52 
53 	reg16 = x86_pci_read_config16(dev, SECSTS);
54 	/* reg16 |= 0xf900; */
55 	x86_pci_write_config16(dev, SECSTS, reg16);
56 }
57 
58 #define PCI_BRIDGE_UPDATE_COMMAND
59 void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
60 {
61 	uint16_t command;
62 
63 	command = x86_pci_read_config16(dev, PCI_COMMAND);
64 	command |= PCI_COMMAND_IO;
65 #ifdef PCI_BRIDGE_UPDATE_COMMAND
66 	/*
67 	 * If we write to PCI_COMMAND, on some systems this will cause the
68 	 * ROM and APICs to become invisible.
69 	 */
70 	debug("%x cmd <- %02x\n", dev, command);
71 	x86_pci_write_config16(dev, PCI_COMMAND, command);
72 #else
73 	printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
74 #endif
75 }
76 
77 void bd82x6x_pci_bus_enable_resources(pci_dev_t dev)
78 {
79 	uint16_t ctrl;
80 
81 	ctrl = x86_pci_read_config16(dev, PCI_BRIDGE_CONTROL);
82 	ctrl |= PCI_COMMAND_IO;
83 	ctrl |= PCI_BRIDGE_CTL_VGA;
84 	debug("%x bridge ctrl <- %04x\n", dev, ctrl);
85 	x86_pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
86 
87 	bd82x6x_pci_dev_enable_resources(dev);
88 }
89 
90 static int bd82x6x_probe(struct udevice *dev)
91 {
92 	const void *blob = gd->fdt_blob;
93 	struct pci_controller *hose;
94 	struct x86_cpu_priv *cpu;
95 	int sata_node, gma_node;
96 	int ret;
97 
98 	hose = pci_bus_to_hose(0);
99 	lpc_enable(PCH_LPC_DEV);
100 	lpc_init(hose, PCH_LPC_DEV);
101 	sata_node = fdtdec_next_compatible(blob, 0,
102 					   COMPAT_INTEL_PANTHERPOINT_AHCI);
103 	if (sata_node < 0) {
104 		debug("%s: Cannot find SATA node\n", __func__);
105 		return -EINVAL;
106 	}
107 	bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node);
108 	bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
109 	bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
110 
111 	cpu = calloc(1, sizeof(*cpu));
112 	if (!cpu)
113 		return -ENOMEM;
114 	model_206ax_init(cpu);
115 
116 	gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA);
117 	if (gma_node < 0) {
118 		debug("%s: Cannot find GMA node\n", __func__);
119 		return -EINVAL;
120 	}
121 	ret = gma_func0_init(PCH_VIDEO_DEV, pci_bus_to_hose(0), blob,
122 			     gma_node);
123 	if (ret)
124 		return ret;
125 
126 	return 0;
127 }
128 
129 int bd82x6x_init(void)
130 {
131 	const void *blob = gd->fdt_blob;
132 	int sata_node;
133 
134 	sata_node = fdtdec_next_compatible(blob, 0,
135 					   COMPAT_INTEL_PANTHERPOINT_AHCI);
136 	if (sata_node < 0) {
137 		debug("%s: Cannot find SATA node\n", __func__);
138 		return -EINVAL;
139 	}
140 
141 	bd82x6x_pci_init(PCH_DEV);
142 	bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node);
143 	northbridge_enable(PCH_DEV);
144 	northbridge_init(PCH_DEV);
145 
146 	return 0;
147 }
148 
149 static const struct udevice_id bd82x6x_ids[] = {
150 	{ .compatible = "intel,bd82x6x" },
151 	{ }
152 };
153 
154 U_BOOT_DRIVER(bd82x6x_drv) = {
155 	.name		= "bd82x6x",
156 	.id		= UCLASS_PCH,
157 	.of_match	= bd82x6x_ids,
158 	.probe		= bd82x6x_probe,
159 };
160