1 /* 2 * Copyright (C) 2014 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <dm.h> 8 #include <errno.h> 9 #include <fdtdec.h> 10 #include <malloc.h> 11 #include <pch.h> 12 #include <asm/lapic.h> 13 #include <asm/pci.h> 14 #include <asm/arch/bd82x6x.h> 15 #include <asm/arch/model_206ax.h> 16 #include <asm/arch/pch.h> 17 #include <asm/arch/sandybridge.h> 18 19 #define BIOS_CTRL 0xdc 20 21 static int bd82x6x_probe(struct udevice *dev) 22 { 23 const void *blob = gd->fdt_blob; 24 struct pci_controller *hose; 25 int sata_node, gma_node; 26 int ret; 27 28 if (!(gd->flags & GD_FLG_RELOC)) 29 return 0; 30 31 hose = pci_bus_to_hose(0); 32 lpc_enable(PCH_LPC_DEV); 33 lpc_init_extra(hose, PCH_LPC_DEV); 34 sata_node = fdtdec_next_compatible(blob, 0, 35 COMPAT_INTEL_PANTHERPOINT_AHCI); 36 if (sata_node < 0) { 37 debug("%s: Cannot find SATA node\n", __func__); 38 return -EINVAL; 39 } 40 bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node); 41 bd82x6x_usb_ehci_init(PCH_EHCI1_DEV); 42 bd82x6x_usb_ehci_init(PCH_EHCI2_DEV); 43 44 gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA); 45 if (gma_node < 0) { 46 debug("%s: Cannot find GMA node\n", __func__); 47 return -EINVAL; 48 } 49 ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev); 50 if (ret) 51 return ret; 52 ret = gma_func0_init(dev, blob, gma_node); 53 if (ret) 54 return ret; 55 56 return 0; 57 } 58 59 static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep) 60 { 61 u32 rcba; 62 63 dm_pci_read_config32(dev, PCH_RCBA, &rcba); 64 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ 65 rcba = rcba & 0xffffc000; 66 *sbasep = rcba + 0x3800; 67 68 return 0; 69 } 70 71 static enum pch_version bd82x6x_pch_get_version(struct udevice *dev) 72 { 73 return PCHV_9; 74 } 75 76 static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect) 77 { 78 uint8_t bios_cntl; 79 80 /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */ 81 dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl); 82 if (protect) { 83 bios_cntl &= ~BIOS_CTRL_BIOSWE; 84 bios_cntl |= BIT(5); 85 } else { 86 bios_cntl |= BIOS_CTRL_BIOSWE; 87 bios_cntl &= ~BIT(5); 88 } 89 dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl); 90 91 return 0; 92 } 93 94 static const struct pch_ops bd82x6x_pch_ops = { 95 .get_sbase = bd82x6x_pch_get_sbase, 96 .get_version = bd82x6x_pch_get_version, 97 .set_spi_protect = bd82x6x_set_spi_protect, 98 }; 99 100 static const struct udevice_id bd82x6x_ids[] = { 101 { .compatible = "intel,bd82x6x" }, 102 { } 103 }; 104 105 U_BOOT_DRIVER(bd82x6x_drv) = { 106 .name = "bd82x6x", 107 .id = UCLASS_PCH, 108 .of_match = bd82x6x_ids, 109 .probe = bd82x6x_probe, 110 .ops = &bd82x6x_pch_ops, 111 }; 112