1 /* 2 * Copyright (C) 2014 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <dm.h> 8 #include <errno.h> 9 #include <fdtdec.h> 10 #include <malloc.h> 11 #include <pch.h> 12 #include <syscon.h> 13 #include <asm/cpu.h> 14 #include <asm/io.h> 15 #include <asm/lapic.h> 16 #include <asm/pci.h> 17 #include <asm/arch/bd82x6x.h> 18 #include <asm/arch/model_206ax.h> 19 #include <asm/arch/pch.h> 20 #include <asm/arch/sandybridge.h> 21 22 #define GPIO_BASE 0x48 23 #define BIOS_CTRL 0xdc 24 25 static int pch_revision_id = -1; 26 static int pch_type = -1; 27 28 /** 29 * pch_silicon_revision() - Read silicon revision ID from the PCH 30 * 31 * @dev: PCH device 32 * @return silicon revision ID 33 */ 34 static int pch_silicon_revision(struct udevice *dev) 35 { 36 u8 val; 37 38 if (pch_revision_id < 0) { 39 dm_pci_read_config8(dev, PCI_REVISION_ID, &val); 40 pch_revision_id = val; 41 } 42 43 return pch_revision_id; 44 } 45 46 int pch_silicon_type(struct udevice *dev) 47 { 48 u8 val; 49 50 if (pch_type < 0) { 51 dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val); 52 pch_type = val; 53 } 54 55 return pch_type; 56 } 57 58 /** 59 * pch_silicon_supported() - Check if a certain revision is supported 60 * 61 * @dev: PCH device 62 * @type: PCH type 63 * @rev: Minimum required resion 64 * @return 0 if not supported, 1 if supported 65 */ 66 static int pch_silicon_supported(struct udevice *dev, int type, int rev) 67 { 68 int cur_type = pch_silicon_type(dev); 69 int cur_rev = pch_silicon_revision(dev); 70 71 switch (type) { 72 case PCH_TYPE_CPT: 73 /* CougarPoint minimum revision */ 74 if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) 75 return 1; 76 /* PantherPoint any revision */ 77 if (cur_type == PCH_TYPE_PPT) 78 return 1; 79 break; 80 81 case PCH_TYPE_PPT: 82 /* PantherPoint minimum revision */ 83 if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) 84 return 1; 85 break; 86 } 87 88 return 0; 89 } 90 91 #define IOBP_RETRY 1000 92 static inline int iobp_poll(void) 93 { 94 unsigned try = IOBP_RETRY; 95 u32 data; 96 97 while (try--) { 98 data = readl(RCB_REG(IOBPS)); 99 if ((data & 1) == 0) 100 return 1; 101 udelay(10); 102 } 103 104 printf("IOBP timeout\n"); 105 return 0; 106 } 107 108 void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, 109 u32 orvalue) 110 { 111 u32 data; 112 113 /* Set the address */ 114 writel(address, RCB_REG(IOBPIRI)); 115 116 /* READ OPCODE */ 117 if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) 118 writel(IOBPS_RW_BX, RCB_REG(IOBPS)); 119 else 120 writel(IOBPS_READ_AX, RCB_REG(IOBPS)); 121 if (!iobp_poll()) 122 return; 123 124 /* Read IOBP data */ 125 data = readl(RCB_REG(IOBPD)); 126 if (!iobp_poll()) 127 return; 128 129 /* Check for successful transaction */ 130 if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) { 131 printf("IOBP read 0x%08x failed\n", address); 132 return; 133 } 134 135 /* Update the data */ 136 data &= andvalue; 137 data |= orvalue; 138 139 /* WRITE OPCODE */ 140 if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) 141 writel(IOBPS_RW_BX, RCB_REG(IOBPS)); 142 else 143 writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); 144 if (!iobp_poll()) 145 return; 146 147 /* Write IOBP data */ 148 writel(data, RCB_REG(IOBPD)); 149 if (!iobp_poll()) 150 return; 151 } 152 153 static int bd82x6x_probe(struct udevice *dev) 154 { 155 struct udevice *gma_dev; 156 int ret; 157 158 if (!(gd->flags & GD_FLG_RELOC)) 159 return 0; 160 161 /* Cause the SATA device to do its init */ 162 uclass_first_device(UCLASS_DISK, &dev); 163 164 ret = syscon_get_by_driver_data(X86_SYSCON_GMA, &gma_dev); 165 if (ret) 166 return ret; 167 ret = gma_func0_init(gma_dev); 168 if (ret) 169 return ret; 170 171 return 0; 172 } 173 174 static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep) 175 { 176 u32 rcba; 177 178 dm_pci_read_config32(dev, PCH_RCBA, &rcba); 179 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ 180 rcba = rcba & 0xffffc000; 181 *sbasep = rcba + 0x3800; 182 183 return 0; 184 } 185 186 static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect) 187 { 188 uint8_t bios_cntl; 189 190 /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */ 191 dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl); 192 if (protect) { 193 bios_cntl &= ~BIOS_CTRL_BIOSWE; 194 bios_cntl |= BIT(5); 195 } else { 196 bios_cntl |= BIOS_CTRL_BIOSWE; 197 bios_cntl &= ~BIT(5); 198 } 199 dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl); 200 201 return 0; 202 } 203 204 static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep) 205 { 206 u32 base; 207 208 /* 209 * GPIO_BASE moved to its current offset with ICH6, but prior to 210 * that it was unused (or undocumented). Check that it looks 211 * okay: not all ones or zeros. 212 * 213 * Note we don't need check bit0 here, because the Tunnel Creek 214 * GPIO base address register bit0 is reserved (read returns 0), 215 * while on the Ivybridge the bit0 is used to indicate it is an 216 * I/O space. 217 */ 218 dm_pci_read_config32(dev, GPIO_BASE, &base); 219 if (base == 0x00000000 || base == 0xffffffff) { 220 debug("%s: unexpected BASE value\n", __func__); 221 return -ENODEV; 222 } 223 224 /* 225 * Okay, I guess we're looking at the right device. The actual 226 * GPIO registers are in the PCI device's I/O space, starting 227 * at the offset that we just read. Bit 0 indicates that it's 228 * an I/O address, not a memory address, so mask that off. 229 */ 230 *gbasep = base & 1 ? base & ~3 : base & ~15; 231 232 return 0; 233 } 234 235 static const struct pch_ops bd82x6x_pch_ops = { 236 .get_spi_base = bd82x6x_pch_get_spi_base, 237 .set_spi_protect = bd82x6x_set_spi_protect, 238 .get_gpio_base = bd82x6x_get_gpio_base, 239 }; 240 241 static const struct udevice_id bd82x6x_ids[] = { 242 { .compatible = "intel,bd82x6x" }, 243 { } 244 }; 245 246 U_BOOT_DRIVER(bd82x6x_drv) = { 247 .name = "bd82x6x", 248 .id = UCLASS_PCH, 249 .of_match = bd82x6x_ids, 250 .probe = bd82x6x_probe, 251 .ops = &bd82x6x_pch_ops, 252 }; 253