1 /* 2 * Copyright (C) 2014 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <dm.h> 8 #include <errno.h> 9 #include <fdtdec.h> 10 #include <malloc.h> 11 #include <pch.h> 12 #include <syscon.h> 13 #include <asm/cpu.h> 14 #include <asm/intel_regs.h> 15 #include <asm/io.h> 16 #include <asm/lapic.h> 17 #include <asm/lpc_common.h> 18 #include <asm/pci.h> 19 #include <asm/arch/bd82x6x.h> 20 #include <asm/arch/model_206ax.h> 21 #include <asm/arch/pch.h> 22 #include <asm/arch/sandybridge.h> 23 24 #define GPIO_BASE 0x48 25 #define BIOS_CTRL 0xdc 26 27 #ifndef CONFIG_HAVE_FSP 28 static int pch_revision_id = -1; 29 static int pch_type = -1; 30 31 /** 32 * pch_silicon_revision() - Read silicon revision ID from the PCH 33 * 34 * @dev: PCH device 35 * @return silicon revision ID 36 */ 37 static int pch_silicon_revision(struct udevice *dev) 38 { 39 u8 val; 40 41 if (pch_revision_id < 0) { 42 dm_pci_read_config8(dev, PCI_REVISION_ID, &val); 43 pch_revision_id = val; 44 } 45 46 return pch_revision_id; 47 } 48 49 int pch_silicon_type(struct udevice *dev) 50 { 51 u8 val; 52 53 if (pch_type < 0) { 54 dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val); 55 pch_type = val; 56 } 57 58 return pch_type; 59 } 60 61 /** 62 * pch_silicon_supported() - Check if a certain revision is supported 63 * 64 * @dev: PCH device 65 * @type: PCH type 66 * @rev: Minimum required resion 67 * @return 0 if not supported, 1 if supported 68 */ 69 static int pch_silicon_supported(struct udevice *dev, int type, int rev) 70 { 71 int cur_type = pch_silicon_type(dev); 72 int cur_rev = pch_silicon_revision(dev); 73 74 switch (type) { 75 case PCH_TYPE_CPT: 76 /* CougarPoint minimum revision */ 77 if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) 78 return 1; 79 /* PantherPoint any revision */ 80 if (cur_type == PCH_TYPE_PPT) 81 return 1; 82 break; 83 84 case PCH_TYPE_PPT: 85 /* PantherPoint minimum revision */ 86 if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) 87 return 1; 88 break; 89 } 90 91 return 0; 92 } 93 94 #define IOBP_RETRY 1000 95 static inline int iobp_poll(void) 96 { 97 unsigned try = IOBP_RETRY; 98 u32 data; 99 100 while (try--) { 101 data = readl(RCB_REG(IOBPS)); 102 if ((data & 1) == 0) 103 return 1; 104 udelay(10); 105 } 106 107 printf("IOBP timeout\n"); 108 return 0; 109 } 110 111 void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, 112 u32 orvalue) 113 { 114 u32 data; 115 116 /* Set the address */ 117 writel(address, RCB_REG(IOBPIRI)); 118 119 /* READ OPCODE */ 120 if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) 121 writel(IOBPS_RW_BX, RCB_REG(IOBPS)); 122 else 123 writel(IOBPS_READ_AX, RCB_REG(IOBPS)); 124 if (!iobp_poll()) 125 return; 126 127 /* Read IOBP data */ 128 data = readl(RCB_REG(IOBPD)); 129 if (!iobp_poll()) 130 return; 131 132 /* Check for successful transaction */ 133 if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) { 134 printf("IOBP read 0x%08x failed\n", address); 135 return; 136 } 137 138 /* Update the data */ 139 data &= andvalue; 140 data |= orvalue; 141 142 /* WRITE OPCODE */ 143 if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) 144 writel(IOBPS_RW_BX, RCB_REG(IOBPS)); 145 else 146 writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); 147 if (!iobp_poll()) 148 return; 149 150 /* Write IOBP data */ 151 writel(data, RCB_REG(IOBPD)); 152 if (!iobp_poll()) 153 return; 154 } 155 156 static int bd82x6x_probe(struct udevice *dev) 157 { 158 struct udevice *gma_dev; 159 int ret; 160 161 if (!(gd->flags & GD_FLG_RELOC)) 162 return 0; 163 164 /* Cause the SATA device to do its init */ 165 uclass_first_device(UCLASS_DISK, &dev); 166 167 ret = syscon_get_by_driver_data(X86_SYSCON_GMA, &gma_dev); 168 if (ret) 169 return ret; 170 ret = gma_func0_init(gma_dev); 171 if (ret) 172 return ret; 173 174 return 0; 175 } 176 #endif /* CONFIG_HAVE_FSP */ 177 178 static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep) 179 { 180 u32 rcba; 181 182 dm_pci_read_config32(dev, PCH_RCBA, &rcba); 183 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ 184 rcba = rcba & 0xffffc000; 185 *sbasep = rcba + 0x3800; 186 187 return 0; 188 } 189 190 static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect) 191 { 192 return lpc_set_spi_protect(dev, BIOS_CTRL, protect); 193 } 194 195 static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep) 196 { 197 u32 base; 198 199 /* 200 * GPIO_BASE moved to its current offset with ICH6, but prior to 201 * that it was unused (or undocumented). Check that it looks 202 * okay: not all ones or zeros. 203 * 204 * Note we don't need check bit0 here, because the Tunnel Creek 205 * GPIO base address register bit0 is reserved (read returns 0), 206 * while on the Ivybridge the bit0 is used to indicate it is an 207 * I/O space. 208 */ 209 dm_pci_read_config32(dev, GPIO_BASE, &base); 210 if (base == 0x00000000 || base == 0xffffffff) { 211 debug("%s: unexpected BASE value\n", __func__); 212 return -ENODEV; 213 } 214 215 /* 216 * Okay, I guess we're looking at the right device. The actual 217 * GPIO registers are in the PCI device's I/O space, starting 218 * at the offset that we just read. Bit 0 indicates that it's 219 * an I/O address, not a memory address, so mask that off. 220 */ 221 *gbasep = base & 1 ? base & ~3 : base & ~15; 222 223 return 0; 224 } 225 226 static const struct pch_ops bd82x6x_pch_ops = { 227 .get_spi_base = bd82x6x_pch_get_spi_base, 228 .set_spi_protect = bd82x6x_set_spi_protect, 229 .get_gpio_base = bd82x6x_get_gpio_base, 230 }; 231 232 static const struct udevice_id bd82x6x_ids[] = { 233 { .compatible = "intel,bd82x6x" }, 234 { } 235 }; 236 237 U_BOOT_DRIVER(bd82x6x_drv) = { 238 .name = "bd82x6x", 239 .id = UCLASS_PCH, 240 .of_match = bd82x6x_ids, 241 #ifndef CONFIG_HAVE_FSP 242 .probe = bd82x6x_probe, 243 #endif 244 .ops = &bd82x6x_pch_ops, 245 }; 246