1 /* 2 * Copyright (C) 2014 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <errno.h> 10 #include <fdtdec.h> 11 #include <malloc.h> 12 #include <asm/lapic.h> 13 #include <asm/pci.h> 14 #include <asm/arch/bd82x6x.h> 15 #include <asm/arch/model_206ax.h> 16 #include <asm/arch/pch.h> 17 #include <asm/arch/sandybridge.h> 18 19 void bd82x6x_pci_init(pci_dev_t dev) 20 { 21 u16 reg16; 22 u8 reg8; 23 24 debug("bd82x6x PCI init.\n"); 25 /* Enable Bus Master */ 26 reg16 = x86_pci_read_config16(dev, PCI_COMMAND); 27 reg16 |= PCI_COMMAND_MASTER; 28 x86_pci_write_config16(dev, PCI_COMMAND, reg16); 29 30 /* This device has no interrupt */ 31 x86_pci_write_config8(dev, INTR, 0xff); 32 33 /* disable parity error response and SERR */ 34 reg16 = x86_pci_read_config16(dev, BCTRL); 35 reg16 &= ~(1 << 0); 36 reg16 &= ~(1 << 1); 37 x86_pci_write_config16(dev, BCTRL, reg16); 38 39 /* Master Latency Count must be set to 0x04! */ 40 reg8 = x86_pci_read_config8(dev, SMLT); 41 reg8 &= 0x07; 42 reg8 |= (0x04 << 3); 43 x86_pci_write_config8(dev, SMLT, reg8); 44 45 /* Will this improve throughput of bus masters? */ 46 x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06); 47 48 /* Clear errors in status registers */ 49 reg16 = x86_pci_read_config16(dev, PSTS); 50 /* reg16 |= 0xf900; */ 51 x86_pci_write_config16(dev, PSTS, reg16); 52 53 reg16 = x86_pci_read_config16(dev, SECSTS); 54 /* reg16 |= 0xf900; */ 55 x86_pci_write_config16(dev, SECSTS, reg16); 56 } 57 58 static int bd82x6x_probe(struct udevice *dev) 59 { 60 const void *blob = gd->fdt_blob; 61 struct pci_controller *hose; 62 struct x86_cpu_priv *cpu; 63 int sata_node, gma_node; 64 int ret; 65 66 hose = pci_bus_to_hose(0); 67 lpc_enable(PCH_LPC_DEV); 68 lpc_init(hose, PCH_LPC_DEV); 69 sata_node = fdtdec_next_compatible(blob, 0, 70 COMPAT_INTEL_PANTHERPOINT_AHCI); 71 if (sata_node < 0) { 72 debug("%s: Cannot find SATA node\n", __func__); 73 return -EINVAL; 74 } 75 bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node); 76 bd82x6x_usb_ehci_init(PCH_EHCI1_DEV); 77 bd82x6x_usb_ehci_init(PCH_EHCI2_DEV); 78 79 cpu = calloc(1, sizeof(*cpu)); 80 if (!cpu) 81 return -ENOMEM; 82 model_206ax_init(cpu); 83 84 gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA); 85 if (gma_node < 0) { 86 debug("%s: Cannot find GMA node\n", __func__); 87 return -EINVAL; 88 } 89 ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev); 90 if (ret) 91 return ret; 92 ret = gma_func0_init(dev, blob, gma_node); 93 if (ret) 94 return ret; 95 96 return 0; 97 } 98 99 int bd82x6x_init(void) 100 { 101 const void *blob = gd->fdt_blob; 102 int sata_node; 103 104 sata_node = fdtdec_next_compatible(blob, 0, 105 COMPAT_INTEL_PANTHERPOINT_AHCI); 106 if (sata_node < 0) { 107 debug("%s: Cannot find SATA node\n", __func__); 108 return -EINVAL; 109 } 110 111 bd82x6x_pci_init(PCH_DEV); 112 bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node); 113 northbridge_enable(PCH_DEV); 114 northbridge_init(PCH_DEV); 115 116 return 0; 117 } 118 119 static const struct udevice_id bd82x6x_ids[] = { 120 { .compatible = "intel,bd82x6x" }, 121 { } 122 }; 123 124 U_BOOT_DRIVER(bd82x6x_drv) = { 125 .name = "bd82x6x", 126 .id = UCLASS_PCH, 127 .of_match = bd82x6x_ids, 128 .probe = bd82x6x_probe, 129 }; 130