1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <errno.h> 10 #include <fdtdec.h> 11 #include <malloc.h> 12 #include <asm/io.h> 13 #include <asm/irq.h> 14 #include <asm/pci.h> 15 #include <asm/pirq_routing.h> 16 #include <asm/tables.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 static struct irq_routing_table *pirq_routing_table; 21 22 bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq) 23 { 24 struct irq_router *priv = dev_get_priv(dev); 25 u8 pirq; 26 int base = priv->link_base; 27 28 if (priv->config == PIRQ_VIA_PCI) 29 dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq); 30 else 31 pirq = readb(priv->ibase + LINK_N2V(link, base)); 32 33 pirq &= 0xf; 34 35 /* IRQ# 0/1/2/8/13 are reserved */ 36 if (pirq < 3 || pirq == 8 || pirq == 13) 37 return false; 38 39 return pirq == irq ? true : false; 40 } 41 42 int pirq_translate_link(struct udevice *dev, int link) 43 { 44 struct irq_router *priv = dev_get_priv(dev); 45 46 return LINK_V2N(link, priv->link_base); 47 } 48 49 void pirq_assign_irq(struct udevice *dev, int link, u8 irq) 50 { 51 struct irq_router *priv = dev_get_priv(dev); 52 int base = priv->link_base; 53 54 /* IRQ# 0/1/2/8/13 are reserved */ 55 if (irq < 3 || irq == 8 || irq == 13) 56 return; 57 58 if (priv->config == PIRQ_VIA_PCI) 59 dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq); 60 else 61 writeb(irq, priv->ibase + LINK_N2V(link, base)); 62 } 63 64 static struct irq_info *check_dup_entry(struct irq_info *slot_base, 65 int entry_num, int bus, int device) 66 { 67 struct irq_info *slot = slot_base; 68 int i; 69 70 for (i = 0; i < entry_num; i++) { 71 if (slot->bus == bus && slot->devfn == (device << 3)) 72 break; 73 slot++; 74 } 75 76 return (i == entry_num) ? NULL : slot; 77 } 78 79 static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot, 80 int bus, int device, int pin, int pirq) 81 { 82 slot->bus = bus; 83 slot->devfn = (device << 3) | 0; 84 slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base); 85 slot->irq[pin - 1].bitmap = priv->irq_mask; 86 } 87 88 static int create_pirq_routing_table(struct udevice *dev) 89 { 90 struct irq_router *priv = dev_get_priv(dev); 91 const void *blob = gd->fdt_blob; 92 int node; 93 int len, count; 94 const u32 *cell; 95 struct irq_routing_table *rt; 96 struct irq_info *slot, *slot_base; 97 int irq_entries = 0; 98 int i; 99 int ret; 100 101 node = dev->of_offset; 102 103 /* extract the bdf from fdt_pci_addr */ 104 priv->bdf = dm_pci_get_bdf(dev->parent); 105 106 ret = fdt_find_string(blob, node, "intel,pirq-config", "pci"); 107 if (!ret) { 108 priv->config = PIRQ_VIA_PCI; 109 } else { 110 ret = fdt_find_string(blob, node, "intel,pirq-config", "ibase"); 111 if (!ret) 112 priv->config = PIRQ_VIA_IBASE; 113 else 114 return -EINVAL; 115 } 116 117 ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1); 118 if (ret == -1) 119 return ret; 120 priv->link_base = ret; 121 122 priv->irq_mask = fdtdec_get_int(blob, node, 123 "intel,pirq-mask", PIRQ_BITMAP); 124 125 if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) { 126 /* Reserve IRQ9 for SCI */ 127 priv->irq_mask &= ~(1 << 9); 128 } 129 130 if (priv->config == PIRQ_VIA_IBASE) { 131 int ibase_off; 132 133 ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0); 134 if (!ibase_off) 135 return -EINVAL; 136 137 /* 138 * Here we assume that the IBASE register has already been 139 * properly configured by U-Boot before. 140 * 141 * By 'valid' we mean: 142 * 1) a valid memory space carved within system memory space 143 * assigned to IBASE register block. 144 * 2) memory range decoding is enabled. 145 * Hence we don't do any santify test here. 146 */ 147 dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase); 148 priv->ibase &= ~0xf; 149 } 150 151 priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit"); 152 priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0); 153 154 cell = fdt_getprop(blob, node, "intel,pirq-routing", &len); 155 if (!cell || len % sizeof(struct pirq_routing)) 156 return -EINVAL; 157 count = len / sizeof(struct pirq_routing); 158 159 rt = calloc(1, sizeof(struct irq_routing_table)); 160 if (!rt) 161 return -ENOMEM; 162 163 /* Populate the PIRQ table fields */ 164 rt->signature = PIRQ_SIGNATURE; 165 rt->version = PIRQ_VERSION; 166 rt->rtr_bus = PCI_BUS(priv->bdf); 167 rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf); 168 rt->rtr_vendor = PCI_VENDOR_ID_INTEL; 169 rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31; 170 171 slot_base = rt->slots; 172 173 /* Now fill in the irq_info entries in the PIRQ table */ 174 for (i = 0; i < count; 175 i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) { 176 struct pirq_routing pr; 177 178 pr.bdf = fdt_addr_to_cpu(cell[0]); 179 pr.pin = fdt_addr_to_cpu(cell[1]); 180 pr.pirq = fdt_addr_to_cpu(cell[2]); 181 182 debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n", 183 i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), 184 PCI_FUNC(pr.bdf), 'A' + pr.pin - 1, 185 'A' + pr.pirq); 186 187 slot = check_dup_entry(slot_base, irq_entries, 188 PCI_BUS(pr.bdf), PCI_DEV(pr.bdf)); 189 if (slot) { 190 debug("found entry for bus %d device %d, ", 191 PCI_BUS(pr.bdf), PCI_DEV(pr.bdf)); 192 193 if (slot->irq[pr.pin - 1].link) { 194 debug("skipping\n"); 195 196 /* 197 * Sanity test on the routed PIRQ pin 198 * 199 * If they don't match, show a warning to tell 200 * there might be something wrong with the PIRQ 201 * routing information in the device tree. 202 */ 203 if (slot->irq[pr.pin - 1].link != 204 LINK_N2V(pr.pirq, priv->link_base)) 205 debug("WARNING: Inconsistent PIRQ routing information\n"); 206 continue; 207 } 208 } else { 209 slot = slot_base + irq_entries++; 210 } 211 debug("writing INT%c\n", 'A' + pr.pin - 1); 212 fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), 213 pr.pin, pr.pirq); 214 } 215 216 rt->size = irq_entries * sizeof(struct irq_info) + 32; 217 218 /* Fix up the table checksum */ 219 rt->checksum = table_compute_checksum(rt, rt->size); 220 221 pirq_routing_table = rt; 222 223 return 0; 224 } 225 226 static void irq_enable_sci(struct udevice *dev) 227 { 228 struct irq_router *priv = dev_get_priv(dev); 229 230 if (priv->actl_8bit) { 231 /* Bit7 must be turned on to enable ACPI */ 232 dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80); 233 } else { 234 /* Write 0 to enable SCI on IRQ9 */ 235 if (priv->config == PIRQ_VIA_PCI) 236 dm_pci_write_config32(dev->parent, priv->actl_addr, 0); 237 else 238 writel(0, priv->ibase + priv->actl_addr); 239 } 240 } 241 242 int irq_router_common_init(struct udevice *dev) 243 { 244 int ret; 245 246 ret = create_pirq_routing_table(dev); 247 if (ret) { 248 debug("Failed to create pirq routing table\n"); 249 return ret; 250 } 251 /* Route PIRQ */ 252 pirq_route_irqs(dev, pirq_routing_table->slots, 253 get_irq_slot_count(pirq_routing_table)); 254 255 if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) 256 irq_enable_sci(dev); 257 258 return 0; 259 } 260 261 int irq_router_probe(struct udevice *dev) 262 { 263 return irq_router_common_init(dev); 264 } 265 266 u32 write_pirq_routing_table(u32 addr) 267 { 268 if (!pirq_routing_table) 269 return addr; 270 271 return copy_pirq_routing_table(addr, pirq_routing_table); 272 } 273 274 static const struct udevice_id irq_router_ids[] = { 275 { .compatible = "intel,irq-router" }, 276 { } 277 }; 278 279 U_BOOT_DRIVER(irq_router_drv) = { 280 .name = "intel_irq", 281 .id = UCLASS_IRQ, 282 .of_match = irq_router_ids, 283 .probe = irq_router_probe, 284 .priv_auto_alloc_size = sizeof(struct irq_router), 285 }; 286 287 UCLASS_DRIVER(irq) = { 288 .id = UCLASS_IRQ, 289 .name = "irq", 290 }; 291