1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * From Coreboot src/southbridge/intel/bd82x6x/me_status.c
4  *
5  * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
6  */
7 
8 #include <common.h>
9 #include <asm/arch/me.h>
10 
11 /* HFS1[3:0] Current Working State Values */
12 static const char *const me_cws_values[] = {
13 	[ME_HFS_CWS_RESET]	= "Reset",
14 	[ME_HFS_CWS_INIT]	= "Initializing",
15 	[ME_HFS_CWS_REC]	= "Recovery",
16 	[ME_HFS_CWS_NORMAL]	= "Normal",
17 	[ME_HFS_CWS_WAIT]	= "Platform Disable Wait",
18 	[ME_HFS_CWS_TRANS]	= "OP State Transition",
19 	[ME_HFS_CWS_INVALID]	= "Invalid CPU Plugged In"
20 };
21 
22 /* HFS1[8:6] Current Operation State Values */
23 static const char *const me_opstate_values[] = {
24 	[ME_HFS_STATE_PREBOOT]	= "Preboot",
25 	[ME_HFS_STATE_M0_UMA]	= "M0 with UMA",
26 	[ME_HFS_STATE_M3]	= "M3 without UMA",
27 	[ME_HFS_STATE_M0]	= "M0 without UMA",
28 	[ME_HFS_STATE_BRINGUP]	= "Bring up",
29 	[ME_HFS_STATE_ERROR]	= "M0 without UMA but with error"
30 };
31 
32 /* HFS[19:16] Current Operation Mode Values */
33 static const char *const me_opmode_values[] = {
34 	[ME_HFS_MODE_NORMAL]	= "Normal",
35 	[ME_HFS_MODE_DEBUG]	= "Debug",
36 	[ME_HFS_MODE_DIS]	= "Soft Temporary Disable",
37 	[ME_HFS_MODE_OVER_JMPR]	= "Security Override via Jumper",
38 	[ME_HFS_MODE_OVER_MEI]	= "Security Override via MEI Message"
39 };
40 
41 /* HFS[15:12] Error Code Values */
42 static const char *const me_error_values[] = {
43 	[ME_HFS_ERROR_NONE]	= "No Error",
44 	[ME_HFS_ERROR_UNCAT]	= "Uncategorized Failure",
45 	[ME_HFS_ERROR_IMAGE]	= "Image Failure",
46 	[ME_HFS_ERROR_DEBUG]	= "Debug Failure"
47 };
48 
49 /* GMES[31:28] ME Progress Code */
50 static const char *const me_progress_values[] = {
51 	[ME_GMES_PHASE_ROM]	= "ROM Phase",
52 	[ME_GMES_PHASE_BUP]	= "BUP Phase",
53 	[ME_GMES_PHASE_UKERNEL]	= "uKernel Phase",
54 	[ME_GMES_PHASE_POLICY]	= "Policy Module",
55 	[ME_GMES_PHASE_MODULE]	= "Module Loading",
56 	[ME_GMES_PHASE_UNKNOWN]	= "Unknown",
57 	[ME_GMES_PHASE_HOST]	= "Host Communication"
58 };
59 
60 /* GMES[27:24] Power Management Event */
61 static const char *const me_pmevent_values[] = {
62 	[0x00] = "Clean Moff->Mx wake",
63 	[0x01] = "Moff->Mx wake after an error",
64 	[0x02] = "Clean global reset",
65 	[0x03] = "Global reset after an error",
66 	[0x04] = "Clean Intel ME reset",
67 	[0x05] = "Intel ME reset due to exception",
68 	[0x06] = "Pseudo-global reset",
69 	[0x07] = "S0/M0->Sx/M3",
70 	[0x08] = "Sx/M3->S0/M0",
71 	[0x09] = "Non-power cycle reset",
72 	[0x0a] = "Power cycle reset through M3",
73 	[0x0b] = "Power cycle reset through Moff",
74 	[0x0c] = "Sx/Mx->Sx/Moff"
75 };
76 
77 /* Progress Code 0 states */
78 static const char *const me_progress_rom_values[] = {
79 	[0x00] = "BEGIN",
80 	[0x06] = "DISABLE"
81 };
82 
83 /* Progress Code 1 states */
84 static const char *const me_progress_bup_values[] = {
85 	[0x00] = "Initialization starts",
86 	[0x01] = "Disable the host wake event",
87 	[0x04] = "Flow determination start process",
88 	[0x08] = "Error reading/matching the VSCC table in the descriptor",
89 	[0x0a] = "Check to see if straps say ME DISABLED",
90 	[0x0b] = "Timeout waiting for PWROK",
91 	[0x0d] = "Possibly handle BUP manufacturing override strap",
92 	[0x11] = "Bringup in M3",
93 	[0x12] = "Bringup in M0",
94 	[0x13] = "Flow detection error",
95 	[0x15] = "M3 clock switching error",
96 	[0x18] = "M3 kernel load",
97 	[0x1c] = "T34 missing - cannot program ICC",
98 	[0x1f] = "Waiting for DID BIOS message",
99 	[0x20] = "Waiting for DID BIOS message failure",
100 	[0x21] = "DID reported an error",
101 	[0x22] = "Enabling UMA",
102 	[0x23] = "Enabling UMA error",
103 	[0x24] = "Sending DID Ack to BIOS",
104 	[0x25] = "Sending DID Ack to BIOS error",
105 	[0x26] = "Switching clocks in M0",
106 	[0x27] = "Switching clocks in M0 error",
107 	[0x28] = "ME in temp disable",
108 	[0x32] = "M0 kernel load",
109 };
110 
111 /* Progress Code 3 states */
112 static const char *const me_progress_policy_values[] = {
113 	[0x00] = "Entery into Policy Module",
114 	[0x03] = "Received S3 entry",
115 	[0x04] = "Received S4 entry",
116 	[0x05] = "Received S5 entry",
117 	[0x06] = "Received UPD entry",
118 	[0x07] = "Received PCR entry",
119 	[0x08] = "Received NPCR entry",
120 	[0x09] = "Received host wake",
121 	[0x0a] = "Received AC<>DC switch",
122 	[0x0b] = "Received DRAM Init Done",
123 	[0x0c] = "VSCC Data not found for flash device",
124 	[0x0d] = "VSCC Table is not valid",
125 	[0x0e] = "Flash Partition Boundary is outside address space",
126 	[0x0f] = "ME cannot access the chipset descriptor region",
127 	[0x10] = "Required VSCC values for flash parts do not match",
128 };
129 
130 
131 /**
132  * _intel_me_status() - Check Intel Management Engine status
133  *
134  * struct hfs:	Firmware status
135  * struct gmes:	Management engine status
136  */
137 static void _intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
138 {
139 	/* Check Current States */
140 	debug("ME: FW Partition Table      : %s\n",
141 	      hfs->fpt_bad ? "BAD" : "OK");
142 	debug("ME: Bringup Loader Failure  : %s\n",
143 	      hfs->ft_bup_ld_flr ? "YES" : "NO");
144 	debug("ME: Firmware Init Complete  : %s\n",
145 	      hfs->fw_init_complete ? "YES" : "NO");
146 	debug("ME: Manufacturing Mode      : %s\n",
147 	      hfs->mfg_mode ? "YES" : "NO");
148 	debug("ME: Boot Options Present    : %s\n",
149 	      hfs->boot_options_present ? "YES" : "NO");
150 	debug("ME: Update In Progress      : %s\n",
151 	      hfs->update_in_progress ? "YES" : "NO");
152 	debug("ME: Current Working State   : %s\n",
153 	      me_cws_values[hfs->working_state]);
154 	debug("ME: Current Operation State : %s\n",
155 	      me_opstate_values[hfs->operation_state]);
156 	debug("ME: Current Operation Mode  : %s\n",
157 	      me_opmode_values[hfs->operation_mode]);
158 	debug("ME: Error Code              : %s\n",
159 	      me_error_values[hfs->error_code]);
160 	debug("ME: Progress Phase          : %s\n",
161 	      me_progress_values[gmes->progress_code]);
162 	debug("ME: Power Management Event  : %s\n",
163 	      me_pmevent_values[gmes->current_pmevent]);
164 
165 	debug("ME: Progress Phase State    : ");
166 	switch (gmes->progress_code) {
167 	case ME_GMES_PHASE_ROM:		/* ROM Phase */
168 		debug("%s", me_progress_rom_values[gmes->current_state]);
169 		break;
170 
171 	case ME_GMES_PHASE_BUP:		/* Bringup Phase */
172 		if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) &&
173 		    me_progress_bup_values[gmes->current_state])
174 			debug("%s",
175 			      me_progress_bup_values[gmes->current_state]);
176 		else
177 			debug("0x%02x", gmes->current_state);
178 		break;
179 
180 	case ME_GMES_PHASE_POLICY:	/* Policy Module Phase */
181 		if (gmes->current_state <
182 				ARRAY_SIZE(me_progress_policy_values) &&
183 		    me_progress_policy_values[gmes->current_state])
184 			debug("%s",
185 			      me_progress_policy_values[gmes->current_state]);
186 		else
187 			debug("0x%02x", gmes->current_state);
188 		break;
189 
190 	case ME_GMES_PHASE_HOST:	/* Host Communication Phase */
191 		if (!gmes->current_state)
192 			debug("Host communication established");
193 		else
194 			debug("0x%02x", gmes->current_state);
195 		break;
196 
197 	default:
198 		debug("Unknown 0x%02x", gmes->current_state);
199 	}
200 	debug("\n");
201 }
202 
203 void intel_me_status(struct udevice *me_dev)
204 {
205 	struct me_hfs hfs;
206 	struct me_gmes gmes;
207 
208 	pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
209 	pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES);
210 
211 	_intel_me_status(&hfs, &gmes);
212 }
213