1 /* 2 * From Coreboot src/southbridge/intel/bd82x6x/me_status.c 3 * 4 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <asm/arch/me.h> 11 12 /* HFS1[3:0] Current Working State Values */ 13 static const char *const me_cws_values[] = { 14 [ME_HFS_CWS_RESET] = "Reset", 15 [ME_HFS_CWS_INIT] = "Initializing", 16 [ME_HFS_CWS_REC] = "Recovery", 17 [ME_HFS_CWS_NORMAL] = "Normal", 18 [ME_HFS_CWS_WAIT] = "Platform Disable Wait", 19 [ME_HFS_CWS_TRANS] = "OP State Transition", 20 [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" 21 }; 22 23 /* HFS1[8:6] Current Operation State Values */ 24 static const char *const me_opstate_values[] = { 25 [ME_HFS_STATE_PREBOOT] = "Preboot", 26 [ME_HFS_STATE_M0_UMA] = "M0 with UMA", 27 [ME_HFS_STATE_M3] = "M3 without UMA", 28 [ME_HFS_STATE_M0] = "M0 without UMA", 29 [ME_HFS_STATE_BRINGUP] = "Bring up", 30 [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" 31 }; 32 33 /* HFS[19:16] Current Operation Mode Values */ 34 static const char *const me_opmode_values[] = { 35 [ME_HFS_MODE_NORMAL] = "Normal", 36 [ME_HFS_MODE_DEBUG] = "Debug", 37 [ME_HFS_MODE_DIS] = "Soft Temporary Disable", 38 [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", 39 [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" 40 }; 41 42 /* HFS[15:12] Error Code Values */ 43 static const char *const me_error_values[] = { 44 [ME_HFS_ERROR_NONE] = "No Error", 45 [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", 46 [ME_HFS_ERROR_IMAGE] = "Image Failure", 47 [ME_HFS_ERROR_DEBUG] = "Debug Failure" 48 }; 49 50 /* GMES[31:28] ME Progress Code */ 51 static const char *const me_progress_values[] = { 52 [ME_GMES_PHASE_ROM] = "ROM Phase", 53 [ME_GMES_PHASE_BUP] = "BUP Phase", 54 [ME_GMES_PHASE_UKERNEL] = "uKernel Phase", 55 [ME_GMES_PHASE_POLICY] = "Policy Module", 56 [ME_GMES_PHASE_MODULE] = "Module Loading", 57 [ME_GMES_PHASE_UNKNOWN] = "Unknown", 58 [ME_GMES_PHASE_HOST] = "Host Communication" 59 }; 60 61 /* GMES[27:24] Power Management Event */ 62 static const char *const me_pmevent_values[] = { 63 [0x00] = "Clean Moff->Mx wake", 64 [0x01] = "Moff->Mx wake after an error", 65 [0x02] = "Clean global reset", 66 [0x03] = "Global reset after an error", 67 [0x04] = "Clean Intel ME reset", 68 [0x05] = "Intel ME reset due to exception", 69 [0x06] = "Pseudo-global reset", 70 [0x07] = "S0/M0->Sx/M3", 71 [0x08] = "Sx/M3->S0/M0", 72 [0x09] = "Non-power cycle reset", 73 [0x0a] = "Power cycle reset through M3", 74 [0x0b] = "Power cycle reset through Moff", 75 [0x0c] = "Sx/Mx->Sx/Moff" 76 }; 77 78 /* Progress Code 0 states */ 79 static const char *const me_progress_rom_values[] = { 80 [0x00] = "BEGIN", 81 [0x06] = "DISABLE" 82 }; 83 84 /* Progress Code 1 states */ 85 static const char *const me_progress_bup_values[] = { 86 [0x00] = "Initialization starts", 87 [0x01] = "Disable the host wake event", 88 [0x04] = "Flow determination start process", 89 [0x08] = "Error reading/matching the VSCC table in the descriptor", 90 [0x0a] = "Check to see if straps say ME DISABLED", 91 [0x0b] = "Timeout waiting for PWROK", 92 [0x0d] = "Possibly handle BUP manufacturing override strap", 93 [0x11] = "Bringup in M3", 94 [0x12] = "Bringup in M0", 95 [0x13] = "Flow detection error", 96 [0x15] = "M3 clock switching error", 97 [0x18] = "M3 kernel load", 98 [0x1c] = "T34 missing - cannot program ICC", 99 [0x1f] = "Waiting for DID BIOS message", 100 [0x20] = "Waiting for DID BIOS message failure", 101 [0x21] = "DID reported an error", 102 [0x22] = "Enabling UMA", 103 [0x23] = "Enabling UMA error", 104 [0x24] = "Sending DID Ack to BIOS", 105 [0x25] = "Sending DID Ack to BIOS error", 106 [0x26] = "Switching clocks in M0", 107 [0x27] = "Switching clocks in M0 error", 108 [0x28] = "ME in temp disable", 109 [0x32] = "M0 kernel load", 110 }; 111 112 /* Progress Code 3 states */ 113 static const char *const me_progress_policy_values[] = { 114 [0x00] = "Entery into Policy Module", 115 [0x03] = "Received S3 entry", 116 [0x04] = "Received S4 entry", 117 [0x05] = "Received S5 entry", 118 [0x06] = "Received UPD entry", 119 [0x07] = "Received PCR entry", 120 [0x08] = "Received NPCR entry", 121 [0x09] = "Received host wake", 122 [0x0a] = "Received AC<>DC switch", 123 [0x0b] = "Received DRAM Init Done", 124 [0x0c] = "VSCC Data not found for flash device", 125 [0x0d] = "VSCC Table is not valid", 126 [0x0e] = "Flash Partition Boundary is outside address space", 127 [0x0f] = "ME cannot access the chipset descriptor region", 128 [0x10] = "Required VSCC values for flash parts do not match", 129 }; 130 131 132 /** 133 * _intel_me_status() - Check Intel Management Engine status 134 * 135 * struct hfs: Firmware status 136 * struct gmes: Management engine status 137 */ 138 static void _intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) 139 { 140 /* Check Current States */ 141 debug("ME: FW Partition Table : %s\n", 142 hfs->fpt_bad ? "BAD" : "OK"); 143 debug("ME: Bringup Loader Failure : %s\n", 144 hfs->ft_bup_ld_flr ? "YES" : "NO"); 145 debug("ME: Firmware Init Complete : %s\n", 146 hfs->fw_init_complete ? "YES" : "NO"); 147 debug("ME: Manufacturing Mode : %s\n", 148 hfs->mfg_mode ? "YES" : "NO"); 149 debug("ME: Boot Options Present : %s\n", 150 hfs->boot_options_present ? "YES" : "NO"); 151 debug("ME: Update In Progress : %s\n", 152 hfs->update_in_progress ? "YES" : "NO"); 153 debug("ME: Current Working State : %s\n", 154 me_cws_values[hfs->working_state]); 155 debug("ME: Current Operation State : %s\n", 156 me_opstate_values[hfs->operation_state]); 157 debug("ME: Current Operation Mode : %s\n", 158 me_opmode_values[hfs->operation_mode]); 159 debug("ME: Error Code : %s\n", 160 me_error_values[hfs->error_code]); 161 debug("ME: Progress Phase : %s\n", 162 me_progress_values[gmes->progress_code]); 163 debug("ME: Power Management Event : %s\n", 164 me_pmevent_values[gmes->current_pmevent]); 165 166 debug("ME: Progress Phase State : "); 167 switch (gmes->progress_code) { 168 case ME_GMES_PHASE_ROM: /* ROM Phase */ 169 debug("%s", me_progress_rom_values[gmes->current_state]); 170 break; 171 172 case ME_GMES_PHASE_BUP: /* Bringup Phase */ 173 if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) && 174 me_progress_bup_values[gmes->current_state]) 175 debug("%s", 176 me_progress_bup_values[gmes->current_state]); 177 else 178 debug("0x%02x", gmes->current_state); 179 break; 180 181 case ME_GMES_PHASE_POLICY: /* Policy Module Phase */ 182 if (gmes->current_state < 183 ARRAY_SIZE(me_progress_policy_values) && 184 me_progress_policy_values[gmes->current_state]) 185 debug("%s", 186 me_progress_policy_values[gmes->current_state]); 187 else 188 debug("0x%02x", gmes->current_state); 189 break; 190 191 case ME_GMES_PHASE_HOST: /* Host Communication Phase */ 192 if (!gmes->current_state) 193 debug("Host communication established"); 194 else 195 debug("0x%02x", gmes->current_state); 196 break; 197 198 default: 199 debug("Unknown 0x%02x", gmes->current_state); 200 } 201 debug("\n"); 202 } 203 204 void intel_me_status(struct udevice *me_dev) 205 { 206 struct me_hfs hfs; 207 struct me_gmes gmes; 208 209 pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS); 210 pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES); 211 212 _intel_me_status(&hfs, &gmes); 213 } 214