1 /* 2 * Copyright (c) 2016 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <errno.h> 10 #include <fdtdec.h> 11 #include <pch.h> 12 #include <pci.h> 13 #include <asm/intel_regs.h> 14 #include <asm/io.h> 15 #include <asm/lpc_common.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 /* Enable Prefetching and Caching */ 20 static void enable_spi_prefetch(struct udevice *pch) 21 { 22 u8 reg8; 23 24 dm_pci_read_config8(pch, 0xdc, ®8); 25 reg8 &= ~(3 << 2); 26 reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ 27 dm_pci_write_config8(pch, 0xdc, reg8); 28 } 29 30 static void enable_port80_on_lpc(struct udevice *pch) 31 { 32 /* Enable port 80 POST on LPC */ 33 dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1); 34 clrbits_le32(RCB_REG(GCS), 4); 35 } 36 37 /** 38 * lpc_early_init() - set up LPC serial ports and other early things 39 * 40 * @dev: LPC device 41 * @return 0 if OK, -ve on error 42 */ 43 int lpc_common_early_init(struct udevice *dev) 44 { 45 struct udevice *pch = dev->parent; 46 struct reg_info { 47 u32 base; 48 u32 size; 49 } values[4], *ptr; 50 int count; 51 int i; 52 53 count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset, 54 "intel,gen-dec", (u32 *)values, 55 sizeof(values) / sizeof(u32)); 56 if (count < 0) 57 return -EINVAL; 58 59 /* Set COM1/COM2 decode range */ 60 dm_pci_write_config16(pch, LPC_IO_DEC, 0x0010); 61 62 /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ 63 dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | MC_LPC_EN | 64 GAMEL_LPC_EN | COMA_LPC_EN); 65 66 /* Write all registers but use 0 if we run out of data */ 67 count = count * sizeof(u32) / sizeof(values[0]); 68 for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) { 69 u32 reg = 0; 70 71 if (i < count) 72 reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16); 73 dm_pci_write_config32(pch, LPC_GENX_DEC(i), reg); 74 } 75 76 enable_spi_prefetch(pch); 77 78 /* This is already done in start.S, but let's do it in C */ 79 enable_port80_on_lpc(pch); 80 81 return 0; 82 } 83 84 int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect) 85 { 86 uint8_t bios_cntl; 87 88 /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */ 89 dm_pci_read_config8(dev, bios_ctrl, &bios_cntl); 90 if (protect) { 91 bios_cntl &= ~BIOS_CTRL_BIOSWE; 92 bios_cntl |= BIT(5); 93 } else { 94 bios_cntl |= BIOS_CTRL_BIOSWE; 95 bios_cntl &= ~BIT(5); 96 } 97 dm_pci_write_config8(dev, bios_ctrl, bios_cntl); 98 99 return 0; 100 } 101