1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * Part of this file is adapted from coreboot 17 * src/arch/x86/lib/cpu.c 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22 #include <common.h> 23 #include <command.h> 24 #include <errno.h> 25 #include <malloc.h> 26 #include <asm/control_regs.h> 27 #include <asm/cpu.h> 28 #include <asm/post.h> 29 #include <asm/processor.h> 30 #include <asm/processor-flags.h> 31 #include <asm/interrupt.h> 32 #include <asm/tables.h> 33 #include <linux/compiler.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 /* 38 * Constructor for a conventional segment GDT (or LDT) entry 39 * This is a macro so it can be used in initialisers 40 */ 41 #define GDT_ENTRY(flags, base, limit) \ 42 ((((base) & 0xff000000ULL) << (56-24)) | \ 43 (((flags) & 0x0000f0ffULL) << 40) | \ 44 (((limit) & 0x000f0000ULL) << (48-16)) | \ 45 (((base) & 0x00ffffffULL) << 16) | \ 46 (((limit) & 0x0000ffffULL))) 47 48 struct gdt_ptr { 49 u16 len; 50 u32 ptr; 51 } __packed; 52 53 struct cpu_device_id { 54 unsigned vendor; 55 unsigned device; 56 }; 57 58 struct cpuinfo_x86 { 59 uint8_t x86; /* CPU family */ 60 uint8_t x86_vendor; /* CPU vendor */ 61 uint8_t x86_model; 62 uint8_t x86_mask; 63 }; 64 65 /* 66 * List of cpu vendor strings along with their normalized 67 * id values. 68 */ 69 static struct { 70 int vendor; 71 const char *name; 72 } x86_vendors[] = { 73 { X86_VENDOR_INTEL, "GenuineIntel", }, 74 { X86_VENDOR_CYRIX, "CyrixInstead", }, 75 { X86_VENDOR_AMD, "AuthenticAMD", }, 76 { X86_VENDOR_UMC, "UMC UMC UMC ", }, 77 { X86_VENDOR_NEXGEN, "NexGenDriven", }, 78 { X86_VENDOR_CENTAUR, "CentaurHauls", }, 79 { X86_VENDOR_RISE, "RiseRiseRise", }, 80 { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, 81 { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, 82 { X86_VENDOR_NSC, "Geode by NSC", }, 83 { X86_VENDOR_SIS, "SiS SiS SiS ", }, 84 }; 85 86 static const char *const x86_vendor_name[] = { 87 [X86_VENDOR_INTEL] = "Intel", 88 [X86_VENDOR_CYRIX] = "Cyrix", 89 [X86_VENDOR_AMD] = "AMD", 90 [X86_VENDOR_UMC] = "UMC", 91 [X86_VENDOR_NEXGEN] = "NexGen", 92 [X86_VENDOR_CENTAUR] = "Centaur", 93 [X86_VENDOR_RISE] = "Rise", 94 [X86_VENDOR_TRANSMETA] = "Transmeta", 95 [X86_VENDOR_NSC] = "NSC", 96 [X86_VENDOR_SIS] = "SiS", 97 }; 98 99 static void load_ds(u32 segment) 100 { 101 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 102 } 103 104 static void load_es(u32 segment) 105 { 106 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 107 } 108 109 static void load_fs(u32 segment) 110 { 111 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 112 } 113 114 static void load_gs(u32 segment) 115 { 116 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 117 } 118 119 static void load_ss(u32 segment) 120 { 121 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 122 } 123 124 static void load_gdt(const u64 *boot_gdt, u16 num_entries) 125 { 126 struct gdt_ptr gdt; 127 128 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; 129 gdt.ptr = (u32)boot_gdt; 130 131 asm volatile("lgdtl %0\n" : : "m" (gdt)); 132 } 133 134 void setup_gdt(gd_t *id, u64 *gdt_addr) 135 { 136 id->arch.gdt = gdt_addr; 137 /* CS: code, read/execute, 4 GB, base 0 */ 138 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); 139 140 /* DS: data, read/write, 4 GB, base 0 */ 141 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); 142 143 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ 144 id->arch.gd_addr = id; 145 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, 146 (ulong)&id->arch.gd_addr, 0xfffff); 147 148 /* 16-bit CS: code, read/execute, 64 kB, base 0 */ 149 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); 150 151 /* 16-bit DS: data, read/write, 64 kB, base 0 */ 152 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); 153 154 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); 155 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); 156 157 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); 158 load_ds(X86_GDT_ENTRY_32BIT_DS); 159 load_es(X86_GDT_ENTRY_32BIT_DS); 160 load_gs(X86_GDT_ENTRY_32BIT_DS); 161 load_ss(X86_GDT_ENTRY_32BIT_DS); 162 load_fs(X86_GDT_ENTRY_32BIT_FS); 163 } 164 165 #ifdef CONFIG_HAVE_FSP 166 /* 167 * Setup FSP execution environment GDT 168 * 169 * Per Intel FSP external architecture specification, before calling any FSP 170 * APIs, we need make sure the system is in flat 32-bit mode and both the code 171 * and data selectors should have full 4GB access range. Here we reuse the one 172 * we used in arch/x86/cpu/start16.S, and reload the segement registers. 173 */ 174 void setup_fsp_gdt(void) 175 { 176 load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4); 177 load_ds(X86_GDT_ENTRY_32BIT_DS); 178 load_ss(X86_GDT_ENTRY_32BIT_DS); 179 load_es(X86_GDT_ENTRY_32BIT_DS); 180 load_fs(X86_GDT_ENTRY_32BIT_DS); 181 load_gs(X86_GDT_ENTRY_32BIT_DS); 182 } 183 #endif 184 185 int __weak x86_cleanup_before_linux(void) 186 { 187 #ifdef CONFIG_BOOTSTAGE_STASH 188 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, 189 CONFIG_BOOTSTAGE_STASH_SIZE); 190 #endif 191 192 return 0; 193 } 194 195 /* 196 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected 197 * by the fact that they preserve the flags across the division of 5/2. 198 * PII and PPro exhibit this behavior too, but they have cpuid available. 199 */ 200 201 /* 202 * Perform the Cyrix 5/2 test. A Cyrix won't change 203 * the flags, while other 486 chips will. 204 */ 205 static inline int test_cyrix_52div(void) 206 { 207 unsigned int test; 208 209 __asm__ __volatile__( 210 "sahf\n\t" /* clear flags (%eax = 0x0005) */ 211 "div %b2\n\t" /* divide 5 by 2 */ 212 "lahf" /* store flags into %ah */ 213 : "=a" (test) 214 : "0" (5), "q" (2) 215 : "cc"); 216 217 /* AH is 0x02 on Cyrix after the divide.. */ 218 return (unsigned char) (test >> 8) == 0x02; 219 } 220 221 /* 222 * Detect a NexGen CPU running without BIOS hypercode new enough 223 * to have CPUID. (Thanks to Herbert Oppmann) 224 */ 225 226 static int deep_magic_nexgen_probe(void) 227 { 228 int ret; 229 230 __asm__ __volatile__ ( 231 " movw $0x5555, %%ax\n" 232 " xorw %%dx,%%dx\n" 233 " movw $2, %%cx\n" 234 " divw %%cx\n" 235 " movl $0, %%eax\n" 236 " jnz 1f\n" 237 " movl $1, %%eax\n" 238 "1:\n" 239 : "=a" (ret) : : "cx", "dx"); 240 return ret; 241 } 242 243 static bool has_cpuid(void) 244 { 245 return flag_is_changeable_p(X86_EFLAGS_ID); 246 } 247 248 static bool has_mtrr(void) 249 { 250 return cpuid_edx(0x00000001) & (1 << 12) ? true : false; 251 } 252 253 static int build_vendor_name(char *vendor_name) 254 { 255 struct cpuid_result result; 256 result = cpuid(0x00000000); 257 unsigned int *name_as_ints = (unsigned int *)vendor_name; 258 259 name_as_ints[0] = result.ebx; 260 name_as_ints[1] = result.edx; 261 name_as_ints[2] = result.ecx; 262 263 return result.eax; 264 } 265 266 static void identify_cpu(struct cpu_device_id *cpu) 267 { 268 char vendor_name[16]; 269 int i; 270 271 vendor_name[0] = '\0'; /* Unset */ 272 cpu->device = 0; /* fix gcc 4.4.4 warning */ 273 274 /* Find the id and vendor_name */ 275 if (!has_cpuid()) { 276 /* Its a 486 if we can modify the AC flag */ 277 if (flag_is_changeable_p(X86_EFLAGS_AC)) 278 cpu->device = 0x00000400; /* 486 */ 279 else 280 cpu->device = 0x00000300; /* 386 */ 281 if ((cpu->device == 0x00000400) && test_cyrix_52div()) { 282 memcpy(vendor_name, "CyrixInstead", 13); 283 /* If we ever care we can enable cpuid here */ 284 } 285 /* Detect NexGen with old hypercode */ 286 else if (deep_magic_nexgen_probe()) 287 memcpy(vendor_name, "NexGenDriven", 13); 288 } 289 if (has_cpuid()) { 290 int cpuid_level; 291 292 cpuid_level = build_vendor_name(vendor_name); 293 vendor_name[12] = '\0'; 294 295 /* Intel-defined flags: level 0x00000001 */ 296 if (cpuid_level >= 0x00000001) { 297 cpu->device = cpuid_eax(0x00000001); 298 } else { 299 /* Have CPUID level 0 only unheard of */ 300 cpu->device = 0x00000400; 301 } 302 } 303 cpu->vendor = X86_VENDOR_UNKNOWN; 304 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { 305 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { 306 cpu->vendor = x86_vendors[i].vendor; 307 break; 308 } 309 } 310 } 311 312 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) 313 { 314 c->x86 = (tfms >> 8) & 0xf; 315 c->x86_model = (tfms >> 4) & 0xf; 316 c->x86_mask = tfms & 0xf; 317 if (c->x86 == 0xf) 318 c->x86 += (tfms >> 20) & 0xff; 319 if (c->x86 >= 0x6) 320 c->x86_model += ((tfms >> 16) & 0xF) << 4; 321 } 322 323 int x86_cpu_init_f(void) 324 { 325 const u32 em_rst = ~X86_CR0_EM; 326 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; 327 328 /* initialize FPU, reset EM, set MP and NE */ 329 asm ("fninit\n" \ 330 "movl %%cr0, %%eax\n" \ 331 "andl %0, %%eax\n" \ 332 "orl %1, %%eax\n" \ 333 "movl %%eax, %%cr0\n" \ 334 : : "i" (em_rst), "i" (mp_ne_set) : "eax"); 335 336 /* identify CPU via cpuid and store the decoded info into gd->arch */ 337 if (has_cpuid()) { 338 struct cpu_device_id cpu; 339 struct cpuinfo_x86 c; 340 341 identify_cpu(&cpu); 342 get_fms(&c, cpu.device); 343 gd->arch.x86 = c.x86; 344 gd->arch.x86_vendor = cpu.vendor; 345 gd->arch.x86_model = c.x86_model; 346 gd->arch.x86_mask = c.x86_mask; 347 gd->arch.x86_device = cpu.device; 348 349 gd->arch.has_mtrr = has_mtrr(); 350 } 351 352 return 0; 353 } 354 355 void x86_enable_caches(void) 356 { 357 unsigned long cr0; 358 359 cr0 = read_cr0(); 360 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); 361 write_cr0(cr0); 362 wbinvd(); 363 } 364 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); 365 366 void x86_disable_caches(void) 367 { 368 unsigned long cr0; 369 370 cr0 = read_cr0(); 371 cr0 |= X86_CR0_NW | X86_CR0_CD; 372 wbinvd(); 373 write_cr0(cr0); 374 wbinvd(); 375 } 376 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); 377 378 int x86_init_cache(void) 379 { 380 enable_caches(); 381 382 return 0; 383 } 384 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 385 386 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 387 { 388 printf("resetting ...\n"); 389 390 /* wait 50 ms */ 391 udelay(50000); 392 disable_interrupts(); 393 reset_cpu(0); 394 395 /*NOTREACHED*/ 396 return 0; 397 } 398 399 void flush_cache(unsigned long dummy1, unsigned long dummy2) 400 { 401 asm("wbinvd\n"); 402 } 403 404 __weak void reset_cpu(ulong addr) 405 { 406 /* Do a hard reset through the chipset's reset control register */ 407 outb(SYS_RST | RST_CPU, PORT_RESET); 408 for (;;) 409 cpu_hlt(); 410 } 411 412 void x86_full_reset(void) 413 { 414 outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET); 415 } 416 417 int dcache_status(void) 418 { 419 return !(read_cr0() & 0x40000000); 420 } 421 422 /* Define these functions to allow ehch-hcd to function */ 423 void flush_dcache_range(unsigned long start, unsigned long stop) 424 { 425 } 426 427 void invalidate_dcache_range(unsigned long start, unsigned long stop) 428 { 429 } 430 431 void dcache_enable(void) 432 { 433 enable_caches(); 434 } 435 436 void dcache_disable(void) 437 { 438 disable_caches(); 439 } 440 441 void icache_enable(void) 442 { 443 } 444 445 void icache_disable(void) 446 { 447 } 448 449 int icache_status(void) 450 { 451 return 1; 452 } 453 454 void cpu_enable_paging_pae(ulong cr3) 455 { 456 __asm__ __volatile__( 457 /* Load the page table address */ 458 "movl %0, %%cr3\n" 459 /* Enable pae */ 460 "movl %%cr4, %%eax\n" 461 "orl $0x00000020, %%eax\n" 462 "movl %%eax, %%cr4\n" 463 /* Enable paging */ 464 "movl %%cr0, %%eax\n" 465 "orl $0x80000000, %%eax\n" 466 "movl %%eax, %%cr0\n" 467 : 468 : "r" (cr3) 469 : "eax"); 470 } 471 472 void cpu_disable_paging_pae(void) 473 { 474 /* Turn off paging */ 475 __asm__ __volatile__ ( 476 /* Disable paging */ 477 "movl %%cr0, %%eax\n" 478 "andl $0x7fffffff, %%eax\n" 479 "movl %%eax, %%cr0\n" 480 /* Disable pae */ 481 "movl %%cr4, %%eax\n" 482 "andl $0xffffffdf, %%eax\n" 483 "movl %%eax, %%cr4\n" 484 : 485 : 486 : "eax"); 487 } 488 489 static bool can_detect_long_mode(void) 490 { 491 return cpuid_eax(0x80000000) > 0x80000000UL; 492 } 493 494 static bool has_long_mode(void) 495 { 496 return cpuid_edx(0x80000001) & (1 << 29) ? true : false; 497 } 498 499 int cpu_has_64bit(void) 500 { 501 return has_cpuid() && can_detect_long_mode() && 502 has_long_mode(); 503 } 504 505 const char *cpu_vendor_name(int vendor) 506 { 507 const char *name; 508 name = "<invalid cpu vendor>"; 509 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && 510 (x86_vendor_name[vendor] != 0)) 511 name = x86_vendor_name[vendor]; 512 513 return name; 514 } 515 516 char *cpu_get_name(char *name) 517 { 518 unsigned int *name_as_ints = (unsigned int *)name; 519 struct cpuid_result regs; 520 char *ptr; 521 int i; 522 523 /* This bit adds up to 48 bytes */ 524 for (i = 0; i < 3; i++) { 525 regs = cpuid(0x80000002 + i); 526 name_as_ints[i * 4 + 0] = regs.eax; 527 name_as_ints[i * 4 + 1] = regs.ebx; 528 name_as_ints[i * 4 + 2] = regs.ecx; 529 name_as_ints[i * 4 + 3] = regs.edx; 530 } 531 name[CPU_MAX_NAME_LEN - 1] = '\0'; 532 533 /* Skip leading spaces. */ 534 ptr = name; 535 while (*ptr == ' ') 536 ptr++; 537 538 return ptr; 539 } 540 541 int default_print_cpuinfo(void) 542 { 543 printf("CPU: %s, vendor %s, device %xh\n", 544 cpu_has_64bit() ? "x86_64" : "x86", 545 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); 546 547 return 0; 548 } 549 550 #define PAGETABLE_SIZE (6 * 4096) 551 552 /** 553 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode 554 * 555 * @pgtable: Pointer to a 24iKB block of memory 556 */ 557 static void build_pagetable(uint32_t *pgtable) 558 { 559 uint i; 560 561 memset(pgtable, '\0', PAGETABLE_SIZE); 562 563 /* Level 4 needs a single entry */ 564 pgtable[0] = (uint32_t)&pgtable[1024] + 7; 565 566 /* Level 3 has one 64-bit entry for each GiB of memory */ 567 for (i = 0; i < 4; i++) { 568 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + 569 0x1000 * i + 7; 570 } 571 572 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ 573 for (i = 0; i < 2048; i++) 574 pgtable[2048 + i * 2] = 0x183 + (i << 21UL); 575 } 576 577 int cpu_jump_to_64bit(ulong setup_base, ulong target) 578 { 579 uint32_t *pgtable; 580 581 pgtable = memalign(4096, PAGETABLE_SIZE); 582 if (!pgtable) 583 return -ENOMEM; 584 585 build_pagetable(pgtable); 586 cpu_call64((ulong)pgtable, setup_base, target); 587 free(pgtable); 588 589 return -EFAULT; 590 } 591 592 void show_boot_progress(int val) 593 { 594 #if MIN_PORT80_KCLOCKS_DELAY 595 /* 596 * Scale the time counter reading to avoid using 64 bit arithmetics. 597 * Can't use get_timer() here becuase it could be not yet 598 * initialized or even implemented. 599 */ 600 if (!gd->arch.tsc_prev) { 601 gd->arch.tsc_base_kclocks = rdtsc() / 1000; 602 gd->arch.tsc_prev = 0; 603 } else { 604 uint32_t now; 605 606 do { 607 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; 608 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); 609 gd->arch.tsc_prev = now; 610 } 611 #endif 612 outb(val, POST_PORT); 613 } 614 615 #ifndef CONFIG_SYS_COREBOOT 616 int last_stage_init(void) 617 { 618 write_tables(); 619 620 return 0; 621 } 622 #endif 623 624 __weak int x86_init_cpus(void) 625 { 626 return 0; 627 } 628 629 int cpu_init_r(void) 630 { 631 return x86_init_cpus(); 632 } 633