1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * Part of this file is adapted from coreboot 17 * src/arch/x86/lib/cpu.c 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22 #include <common.h> 23 #include <command.h> 24 #include <errno.h> 25 #include <malloc.h> 26 #include <asm/control_regs.h> 27 #include <asm/cpu.h> 28 #include <asm/post.h> 29 #include <asm/processor.h> 30 #include <asm/processor-flags.h> 31 #include <asm/interrupt.h> 32 #include <linux/compiler.h> 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 /* 37 * Constructor for a conventional segment GDT (or LDT) entry 38 * This is a macro so it can be used in initialisers 39 */ 40 #define GDT_ENTRY(flags, base, limit) \ 41 ((((base) & 0xff000000ULL) << (56-24)) | \ 42 (((flags) & 0x0000f0ffULL) << 40) | \ 43 (((limit) & 0x000f0000ULL) << (48-16)) | \ 44 (((base) & 0x00ffffffULL) << 16) | \ 45 (((limit) & 0x0000ffffULL))) 46 47 struct gdt_ptr { 48 u16 len; 49 u32 ptr; 50 } __packed; 51 52 struct cpu_device_id { 53 unsigned vendor; 54 unsigned device; 55 }; 56 57 struct cpuinfo_x86 { 58 uint8_t x86; /* CPU family */ 59 uint8_t x86_vendor; /* CPU vendor */ 60 uint8_t x86_model; 61 uint8_t x86_mask; 62 }; 63 64 /* 65 * List of cpu vendor strings along with their normalized 66 * id values. 67 */ 68 static struct { 69 int vendor; 70 const char *name; 71 } x86_vendors[] = { 72 { X86_VENDOR_INTEL, "GenuineIntel", }, 73 { X86_VENDOR_CYRIX, "CyrixInstead", }, 74 { X86_VENDOR_AMD, "AuthenticAMD", }, 75 { X86_VENDOR_UMC, "UMC UMC UMC ", }, 76 { X86_VENDOR_NEXGEN, "NexGenDriven", }, 77 { X86_VENDOR_CENTAUR, "CentaurHauls", }, 78 { X86_VENDOR_RISE, "RiseRiseRise", }, 79 { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, 80 { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, 81 { X86_VENDOR_NSC, "Geode by NSC", }, 82 { X86_VENDOR_SIS, "SiS SiS SiS ", }, 83 }; 84 85 static const char *const x86_vendor_name[] = { 86 [X86_VENDOR_INTEL] = "Intel", 87 [X86_VENDOR_CYRIX] = "Cyrix", 88 [X86_VENDOR_AMD] = "AMD", 89 [X86_VENDOR_UMC] = "UMC", 90 [X86_VENDOR_NEXGEN] = "NexGen", 91 [X86_VENDOR_CENTAUR] = "Centaur", 92 [X86_VENDOR_RISE] = "Rise", 93 [X86_VENDOR_TRANSMETA] = "Transmeta", 94 [X86_VENDOR_NSC] = "NSC", 95 [X86_VENDOR_SIS] = "SiS", 96 }; 97 98 static void load_ds(u32 segment) 99 { 100 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 101 } 102 103 static void load_es(u32 segment) 104 { 105 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 106 } 107 108 static void load_fs(u32 segment) 109 { 110 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 111 } 112 113 static void load_gs(u32 segment) 114 { 115 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 116 } 117 118 static void load_ss(u32 segment) 119 { 120 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 121 } 122 123 static void load_gdt(const u64 *boot_gdt, u16 num_entries) 124 { 125 struct gdt_ptr gdt; 126 127 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; 128 gdt.ptr = (u32)boot_gdt; 129 130 asm volatile("lgdtl %0\n" : : "m" (gdt)); 131 } 132 133 void setup_gdt(gd_t *id, u64 *gdt_addr) 134 { 135 /* CS: code, read/execute, 4 GB, base 0 */ 136 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); 137 138 /* DS: data, read/write, 4 GB, base 0 */ 139 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); 140 141 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ 142 id->arch.gd_addr = id; 143 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, 144 (ulong)&id->arch.gd_addr, 0xfffff); 145 146 /* 16-bit CS: code, read/execute, 64 kB, base 0 */ 147 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); 148 149 /* 16-bit DS: data, read/write, 64 kB, base 0 */ 150 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); 151 152 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); 153 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); 154 155 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); 156 load_ds(X86_GDT_ENTRY_32BIT_DS); 157 load_es(X86_GDT_ENTRY_32BIT_DS); 158 load_gs(X86_GDT_ENTRY_32BIT_DS); 159 load_ss(X86_GDT_ENTRY_32BIT_DS); 160 load_fs(X86_GDT_ENTRY_32BIT_FS); 161 } 162 163 int __weak x86_cleanup_before_linux(void) 164 { 165 #ifdef CONFIG_BOOTSTAGE_STASH 166 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH, 167 CONFIG_BOOTSTAGE_STASH_SIZE); 168 #endif 169 170 return 0; 171 } 172 173 /* 174 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected 175 * by the fact that they preserve the flags across the division of 5/2. 176 * PII and PPro exhibit this behavior too, but they have cpuid available. 177 */ 178 179 /* 180 * Perform the Cyrix 5/2 test. A Cyrix won't change 181 * the flags, while other 486 chips will. 182 */ 183 static inline int test_cyrix_52div(void) 184 { 185 unsigned int test; 186 187 __asm__ __volatile__( 188 "sahf\n\t" /* clear flags (%eax = 0x0005) */ 189 "div %b2\n\t" /* divide 5 by 2 */ 190 "lahf" /* store flags into %ah */ 191 : "=a" (test) 192 : "0" (5), "q" (2) 193 : "cc"); 194 195 /* AH is 0x02 on Cyrix after the divide.. */ 196 return (unsigned char) (test >> 8) == 0x02; 197 } 198 199 /* 200 * Detect a NexGen CPU running without BIOS hypercode new enough 201 * to have CPUID. (Thanks to Herbert Oppmann) 202 */ 203 204 static int deep_magic_nexgen_probe(void) 205 { 206 int ret; 207 208 __asm__ __volatile__ ( 209 " movw $0x5555, %%ax\n" 210 " xorw %%dx,%%dx\n" 211 " movw $2, %%cx\n" 212 " divw %%cx\n" 213 " movl $0, %%eax\n" 214 " jnz 1f\n" 215 " movl $1, %%eax\n" 216 "1:\n" 217 : "=a" (ret) : : "cx", "dx"); 218 return ret; 219 } 220 221 static bool has_cpuid(void) 222 { 223 return flag_is_changeable_p(X86_EFLAGS_ID); 224 } 225 226 static int build_vendor_name(char *vendor_name) 227 { 228 struct cpuid_result result; 229 result = cpuid(0x00000000); 230 unsigned int *name_as_ints = (unsigned int *)vendor_name; 231 232 name_as_ints[0] = result.ebx; 233 name_as_ints[1] = result.edx; 234 name_as_ints[2] = result.ecx; 235 236 return result.eax; 237 } 238 239 static void identify_cpu(struct cpu_device_id *cpu) 240 { 241 char vendor_name[16]; 242 int i; 243 244 vendor_name[0] = '\0'; /* Unset */ 245 cpu->device = 0; /* fix gcc 4.4.4 warning */ 246 247 /* Find the id and vendor_name */ 248 if (!has_cpuid()) { 249 /* Its a 486 if we can modify the AC flag */ 250 if (flag_is_changeable_p(X86_EFLAGS_AC)) 251 cpu->device = 0x00000400; /* 486 */ 252 else 253 cpu->device = 0x00000300; /* 386 */ 254 if ((cpu->device == 0x00000400) && test_cyrix_52div()) { 255 memcpy(vendor_name, "CyrixInstead", 13); 256 /* If we ever care we can enable cpuid here */ 257 } 258 /* Detect NexGen with old hypercode */ 259 else if (deep_magic_nexgen_probe()) 260 memcpy(vendor_name, "NexGenDriven", 13); 261 } 262 if (has_cpuid()) { 263 int cpuid_level; 264 265 cpuid_level = build_vendor_name(vendor_name); 266 vendor_name[12] = '\0'; 267 268 /* Intel-defined flags: level 0x00000001 */ 269 if (cpuid_level >= 0x00000001) { 270 cpu->device = cpuid_eax(0x00000001); 271 } else { 272 /* Have CPUID level 0 only unheard of */ 273 cpu->device = 0x00000400; 274 } 275 } 276 cpu->vendor = X86_VENDOR_UNKNOWN; 277 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { 278 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { 279 cpu->vendor = x86_vendors[i].vendor; 280 break; 281 } 282 } 283 } 284 285 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) 286 { 287 c->x86 = (tfms >> 8) & 0xf; 288 c->x86_model = (tfms >> 4) & 0xf; 289 c->x86_mask = tfms & 0xf; 290 if (c->x86 == 0xf) 291 c->x86 += (tfms >> 20) & 0xff; 292 if (c->x86 >= 0x6) 293 c->x86_model += ((tfms >> 16) & 0xF) << 4; 294 } 295 296 int x86_cpu_init_f(void) 297 { 298 const u32 em_rst = ~X86_CR0_EM; 299 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; 300 301 /* initialize FPU, reset EM, set MP and NE */ 302 asm ("fninit\n" \ 303 "movl %%cr0, %%eax\n" \ 304 "andl %0, %%eax\n" \ 305 "orl %1, %%eax\n" \ 306 "movl %%eax, %%cr0\n" \ 307 : : "i" (em_rst), "i" (mp_ne_set) : "eax"); 308 309 /* identify CPU via cpuid and store the decoded info into gd->arch */ 310 if (has_cpuid()) { 311 struct cpu_device_id cpu; 312 struct cpuinfo_x86 c; 313 314 identify_cpu(&cpu); 315 get_fms(&c, cpu.device); 316 gd->arch.x86 = c.x86; 317 gd->arch.x86_vendor = cpu.vendor; 318 gd->arch.x86_model = c.x86_model; 319 gd->arch.x86_mask = c.x86_mask; 320 gd->arch.x86_device = cpu.device; 321 } 322 323 return 0; 324 } 325 326 void x86_enable_caches(void) 327 { 328 unsigned long cr0; 329 330 cr0 = read_cr0(); 331 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); 332 write_cr0(cr0); 333 wbinvd(); 334 } 335 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); 336 337 void x86_disable_caches(void) 338 { 339 unsigned long cr0; 340 341 cr0 = read_cr0(); 342 cr0 |= X86_CR0_NW | X86_CR0_CD; 343 wbinvd(); 344 write_cr0(cr0); 345 wbinvd(); 346 } 347 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); 348 349 int x86_init_cache(void) 350 { 351 enable_caches(); 352 353 return 0; 354 } 355 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 356 357 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 358 { 359 printf("resetting ...\n"); 360 361 /* wait 50 ms */ 362 udelay(50000); 363 disable_interrupts(); 364 reset_cpu(0); 365 366 /*NOTREACHED*/ 367 return 0; 368 } 369 370 void flush_cache(unsigned long dummy1, unsigned long dummy2) 371 { 372 asm("wbinvd\n"); 373 } 374 375 void __attribute__ ((regparm(0))) generate_gpf(void); 376 377 /* segment 0x70 is an arbitrary segment which does not exist */ 378 asm(".globl generate_gpf\n" 379 ".hidden generate_gpf\n" 380 ".type generate_gpf, @function\n" 381 "generate_gpf:\n" 382 "ljmp $0x70, $0x47114711\n"); 383 384 __weak void reset_cpu(ulong addr) 385 { 386 printf("Resetting using x86 Triple Fault\n"); 387 set_vector(13, generate_gpf); /* general protection fault handler */ 388 set_vector(8, generate_gpf); /* double fault handler */ 389 generate_gpf(); /* start the show */ 390 } 391 392 int dcache_status(void) 393 { 394 return !(read_cr0() & 0x40000000); 395 } 396 397 /* Define these functions to allow ehch-hcd to function */ 398 void flush_dcache_range(unsigned long start, unsigned long stop) 399 { 400 } 401 402 void invalidate_dcache_range(unsigned long start, unsigned long stop) 403 { 404 } 405 406 void dcache_enable(void) 407 { 408 enable_caches(); 409 } 410 411 void dcache_disable(void) 412 { 413 disable_caches(); 414 } 415 416 void icache_enable(void) 417 { 418 } 419 420 void icache_disable(void) 421 { 422 } 423 424 int icache_status(void) 425 { 426 return 1; 427 } 428 429 void cpu_enable_paging_pae(ulong cr3) 430 { 431 __asm__ __volatile__( 432 /* Load the page table address */ 433 "movl %0, %%cr3\n" 434 /* Enable pae */ 435 "movl %%cr4, %%eax\n" 436 "orl $0x00000020, %%eax\n" 437 "movl %%eax, %%cr4\n" 438 /* Enable paging */ 439 "movl %%cr0, %%eax\n" 440 "orl $0x80000000, %%eax\n" 441 "movl %%eax, %%cr0\n" 442 : 443 : "r" (cr3) 444 : "eax"); 445 } 446 447 void cpu_disable_paging_pae(void) 448 { 449 /* Turn off paging */ 450 __asm__ __volatile__ ( 451 /* Disable paging */ 452 "movl %%cr0, %%eax\n" 453 "andl $0x7fffffff, %%eax\n" 454 "movl %%eax, %%cr0\n" 455 /* Disable pae */ 456 "movl %%cr4, %%eax\n" 457 "andl $0xffffffdf, %%eax\n" 458 "movl %%eax, %%cr4\n" 459 : 460 : 461 : "eax"); 462 } 463 464 static bool can_detect_long_mode(void) 465 { 466 return cpuid_eax(0x80000000) > 0x80000000UL; 467 } 468 469 static bool has_long_mode(void) 470 { 471 return cpuid_edx(0x80000001) & (1 << 29) ? true : false; 472 } 473 474 int cpu_has_64bit(void) 475 { 476 return has_cpuid() && can_detect_long_mode() && 477 has_long_mode(); 478 } 479 480 const char *cpu_vendor_name(int vendor) 481 { 482 const char *name; 483 name = "<invalid cpu vendor>"; 484 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && 485 (x86_vendor_name[vendor] != 0)) 486 name = x86_vendor_name[vendor]; 487 488 return name; 489 } 490 491 char *cpu_get_name(char *name) 492 { 493 unsigned int *name_as_ints = (unsigned int *)name; 494 struct cpuid_result regs; 495 char *ptr; 496 int i; 497 498 /* This bit adds up to 48 bytes */ 499 for (i = 0; i < 3; i++) { 500 regs = cpuid(0x80000002 + i); 501 name_as_ints[i * 4 + 0] = regs.eax; 502 name_as_ints[i * 4 + 1] = regs.ebx; 503 name_as_ints[i * 4 + 2] = regs.ecx; 504 name_as_ints[i * 4 + 3] = regs.edx; 505 } 506 name[CPU_MAX_NAME_LEN - 1] = '\0'; 507 508 /* Skip leading spaces. */ 509 ptr = name; 510 while (*ptr == ' ') 511 ptr++; 512 513 return ptr; 514 } 515 516 int default_print_cpuinfo(void) 517 { 518 printf("CPU: %s, vendor %s, device %xh\n", 519 cpu_has_64bit() ? "x86_64" : "x86", 520 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); 521 522 return 0; 523 } 524 525 #define PAGETABLE_SIZE (6 * 4096) 526 527 /** 528 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode 529 * 530 * @pgtable: Pointer to a 24iKB block of memory 531 */ 532 static void build_pagetable(uint32_t *pgtable) 533 { 534 uint i; 535 536 memset(pgtable, '\0', PAGETABLE_SIZE); 537 538 /* Level 4 needs a single entry */ 539 pgtable[0] = (uint32_t)&pgtable[1024] + 7; 540 541 /* Level 3 has one 64-bit entry for each GiB of memory */ 542 for (i = 0; i < 4; i++) { 543 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + 544 0x1000 * i + 7; 545 } 546 547 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ 548 for (i = 0; i < 2048; i++) 549 pgtable[2048 + i * 2] = 0x183 + (i << 21UL); 550 } 551 552 int cpu_jump_to_64bit(ulong setup_base, ulong target) 553 { 554 uint32_t *pgtable; 555 556 pgtable = memalign(4096, PAGETABLE_SIZE); 557 if (!pgtable) 558 return -ENOMEM; 559 560 build_pagetable(pgtable); 561 cpu_call64((ulong)pgtable, setup_base, target); 562 free(pgtable); 563 564 return -EFAULT; 565 } 566 567 void show_boot_progress(int val) 568 { 569 #if MIN_PORT80_KCLOCKS_DELAY 570 /* 571 * Scale the time counter reading to avoid using 64 bit arithmetics. 572 * Can't use get_timer() here becuase it could be not yet 573 * initialized or even implemented. 574 */ 575 if (!gd->arch.tsc_prev) { 576 gd->arch.tsc_base_kclocks = rdtsc() / 1000; 577 gd->arch.tsc_prev = 0; 578 } else { 579 uint32_t now; 580 581 do { 582 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; 583 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); 584 gd->arch.tsc_prev = now; 585 } 586 #endif 587 outb(val, POST_PORT); 588 } 589