xref: /openbmc/u-boot/arch/x86/cpu/cpu.c (revision a5dec5a5) 
1 /*
2  * (C) Copyright 2008-2011
3  * Graeme Russ, <graeme.russ@gmail.com>
4  *
5  * (C) Copyright 2002
6  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
7  *
8  * (C) Copyright 2002
9  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10  * Marius Groeger <mgroeger@sysgo.de>
11  *
12  * (C) Copyright 2002
13  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14  * Alex Zuepke <azu@sysgo.de>
15  *
16  * Part of this file is adapted from coreboot
17  * src/arch/x86/lib/cpu.c
18  *
19  * SPDX-License-Identifier:	GPL-2.0+
20  */
21 
22 #include <common.h>
23 #include <command.h>
24 #include <errno.h>
25 #include <malloc.h>
26 #include <asm/control_regs.h>
27 #include <asm/cpu.h>
28 #include <asm/post.h>
29 #include <asm/processor.h>
30 #include <asm/processor-flags.h>
31 #include <asm/interrupt.h>
32 #include <linux/compiler.h>
33 
34 DECLARE_GLOBAL_DATA_PTR;
35 
36 /*
37  * Constructor for a conventional segment GDT (or LDT) entry
38  * This is a macro so it can be used in initialisers
39  */
40 #define GDT_ENTRY(flags, base, limit)			\
41 	((((base)  & 0xff000000ULL) << (56-24)) |	\
42 	 (((flags) & 0x0000f0ffULL) << 40) |		\
43 	 (((limit) & 0x000f0000ULL) << (48-16)) |	\
44 	 (((base)  & 0x00ffffffULL) << 16) |		\
45 	 (((limit) & 0x0000ffffULL)))
46 
47 struct gdt_ptr {
48 	u16 len;
49 	u32 ptr;
50 } __packed;
51 
52 struct cpu_device_id {
53 	unsigned vendor;
54 	unsigned device;
55 };
56 
57 struct cpuinfo_x86 {
58 	uint8_t x86;            /* CPU family */
59 	uint8_t x86_vendor;     /* CPU vendor */
60 	uint8_t x86_model;
61 	uint8_t x86_mask;
62 };
63 
64 /*
65  * List of cpu vendor strings along with their normalized
66  * id values.
67  */
68 static struct {
69 	int vendor;
70 	const char *name;
71 } x86_vendors[] = {
72 	{ X86_VENDOR_INTEL,     "GenuineIntel", },
73 	{ X86_VENDOR_CYRIX,     "CyrixInstead", },
74 	{ X86_VENDOR_AMD,       "AuthenticAMD", },
75 	{ X86_VENDOR_UMC,       "UMC UMC UMC ", },
76 	{ X86_VENDOR_NEXGEN,    "NexGenDriven", },
77 	{ X86_VENDOR_CENTAUR,   "CentaurHauls", },
78 	{ X86_VENDOR_RISE,      "RiseRiseRise", },
79 	{ X86_VENDOR_TRANSMETA, "GenuineTMx86", },
80 	{ X86_VENDOR_TRANSMETA, "TransmetaCPU", },
81 	{ X86_VENDOR_NSC,       "Geode by NSC", },
82 	{ X86_VENDOR_SIS,       "SiS SiS SiS ", },
83 };
84 
85 static const char *const x86_vendor_name[] = {
86 	[X86_VENDOR_INTEL]     = "Intel",
87 	[X86_VENDOR_CYRIX]     = "Cyrix",
88 	[X86_VENDOR_AMD]       = "AMD",
89 	[X86_VENDOR_UMC]       = "UMC",
90 	[X86_VENDOR_NEXGEN]    = "NexGen",
91 	[X86_VENDOR_CENTAUR]   = "Centaur",
92 	[X86_VENDOR_RISE]      = "Rise",
93 	[X86_VENDOR_TRANSMETA] = "Transmeta",
94 	[X86_VENDOR_NSC]       = "NSC",
95 	[X86_VENDOR_SIS]       = "SiS",
96 };
97 
98 static void load_ds(u32 segment)
99 {
100 	asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
101 }
102 
103 static void load_es(u32 segment)
104 {
105 	asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
106 }
107 
108 static void load_fs(u32 segment)
109 {
110 	asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
111 }
112 
113 static void load_gs(u32 segment)
114 {
115 	asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
116 }
117 
118 static void load_ss(u32 segment)
119 {
120 	asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
121 }
122 
123 static void load_gdt(const u64 *boot_gdt, u16 num_entries)
124 {
125 	struct gdt_ptr gdt;
126 
127 	gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
128 	gdt.ptr = (u32)boot_gdt;
129 
130 	asm volatile("lgdtl %0\n" : : "m" (gdt));
131 }
132 
133 void setup_gdt(gd_t *id, u64 *gdt_addr)
134 {
135 	/* CS: code, read/execute, 4 GB, base 0 */
136 	gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
137 
138 	/* DS: data, read/write, 4 GB, base 0 */
139 	gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
140 
141 	/* FS: data, read/write, 4 GB, base (Global Data Pointer) */
142 	id->arch.gd_addr = id;
143 	gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
144 		     (ulong)&id->arch.gd_addr, 0xfffff);
145 
146 	/* 16-bit CS: code, read/execute, 64 kB, base 0 */
147 	gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
148 
149 	/* 16-bit DS: data, read/write, 64 kB, base 0 */
150 	gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
151 
152 	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
153 	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
154 
155 	load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
156 	load_ds(X86_GDT_ENTRY_32BIT_DS);
157 	load_es(X86_GDT_ENTRY_32BIT_DS);
158 	load_gs(X86_GDT_ENTRY_32BIT_DS);
159 	load_ss(X86_GDT_ENTRY_32BIT_DS);
160 	load_fs(X86_GDT_ENTRY_32BIT_FS);
161 }
162 
163 int __weak x86_cleanup_before_linux(void)
164 {
165 #ifdef CONFIG_BOOTSTAGE_STASH
166 	bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH,
167 			CONFIG_BOOTSTAGE_STASH_SIZE);
168 #endif
169 
170 	return 0;
171 }
172 
173 /*
174  * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
175  * by the fact that they preserve the flags across the division of 5/2.
176  * PII and PPro exhibit this behavior too, but they have cpuid available.
177  */
178 
179 /*
180  * Perform the Cyrix 5/2 test. A Cyrix won't change
181  * the flags, while other 486 chips will.
182  */
183 static inline int test_cyrix_52div(void)
184 {
185 	unsigned int test;
186 
187 	__asm__ __volatile__(
188 	     "sahf\n\t"		/* clear flags (%eax = 0x0005) */
189 	     "div %b2\n\t"	/* divide 5 by 2 */
190 	     "lahf"		/* store flags into %ah */
191 	     : "=a" (test)
192 	     : "0" (5), "q" (2)
193 	     : "cc");
194 
195 	/* AH is 0x02 on Cyrix after the divide.. */
196 	return (unsigned char) (test >> 8) == 0x02;
197 }
198 
199 /*
200  *	Detect a NexGen CPU running without BIOS hypercode new enough
201  *	to have CPUID. (Thanks to Herbert Oppmann)
202  */
203 
204 static int deep_magic_nexgen_probe(void)
205 {
206 	int ret;
207 
208 	__asm__ __volatile__ (
209 		"	movw	$0x5555, %%ax\n"
210 		"	xorw	%%dx,%%dx\n"
211 		"	movw	$2, %%cx\n"
212 		"	divw	%%cx\n"
213 		"	movl	$0, %%eax\n"
214 		"	jnz	1f\n"
215 		"	movl	$1, %%eax\n"
216 		"1:\n"
217 		: "=a" (ret) : : "cx", "dx");
218 	return  ret;
219 }
220 
221 static bool has_cpuid(void)
222 {
223 	return flag_is_changeable_p(X86_EFLAGS_ID);
224 }
225 
226 static bool has_mtrr(void)
227 {
228 	return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
229 }
230 
231 static int build_vendor_name(char *vendor_name)
232 {
233 	struct cpuid_result result;
234 	result = cpuid(0x00000000);
235 	unsigned int *name_as_ints = (unsigned int *)vendor_name;
236 
237 	name_as_ints[0] = result.ebx;
238 	name_as_ints[1] = result.edx;
239 	name_as_ints[2] = result.ecx;
240 
241 	return result.eax;
242 }
243 
244 static void identify_cpu(struct cpu_device_id *cpu)
245 {
246 	char vendor_name[16];
247 	int i;
248 
249 	vendor_name[0] = '\0'; /* Unset */
250 	cpu->device = 0; /* fix gcc 4.4.4 warning */
251 
252 	/* Find the id and vendor_name */
253 	if (!has_cpuid()) {
254 		/* Its a 486 if we can modify the AC flag */
255 		if (flag_is_changeable_p(X86_EFLAGS_AC))
256 			cpu->device = 0x00000400; /* 486 */
257 		else
258 			cpu->device = 0x00000300; /* 386 */
259 		if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
260 			memcpy(vendor_name, "CyrixInstead", 13);
261 			/* If we ever care we can enable cpuid here */
262 		}
263 		/* Detect NexGen with old hypercode */
264 		else if (deep_magic_nexgen_probe())
265 			memcpy(vendor_name, "NexGenDriven", 13);
266 	}
267 	if (has_cpuid()) {
268 		int  cpuid_level;
269 
270 		cpuid_level = build_vendor_name(vendor_name);
271 		vendor_name[12] = '\0';
272 
273 		/* Intel-defined flags: level 0x00000001 */
274 		if (cpuid_level >= 0x00000001) {
275 			cpu->device = cpuid_eax(0x00000001);
276 		} else {
277 			/* Have CPUID level 0 only unheard of */
278 			cpu->device = 0x00000400;
279 		}
280 	}
281 	cpu->vendor = X86_VENDOR_UNKNOWN;
282 	for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
283 		if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
284 			cpu->vendor = x86_vendors[i].vendor;
285 			break;
286 		}
287 	}
288 }
289 
290 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
291 {
292 	c->x86 = (tfms >> 8) & 0xf;
293 	c->x86_model = (tfms >> 4) & 0xf;
294 	c->x86_mask = tfms & 0xf;
295 	if (c->x86 == 0xf)
296 		c->x86 += (tfms >> 20) & 0xff;
297 	if (c->x86 >= 0x6)
298 		c->x86_model += ((tfms >> 16) & 0xF) << 4;
299 }
300 
301 int x86_cpu_init_f(void)
302 {
303 	const u32 em_rst = ~X86_CR0_EM;
304 	const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
305 
306 	/* initialize FPU, reset EM, set MP and NE */
307 	asm ("fninit\n" \
308 	     "movl %%cr0, %%eax\n" \
309 	     "andl %0, %%eax\n" \
310 	     "orl  %1, %%eax\n" \
311 	     "movl %%eax, %%cr0\n" \
312 	     : : "i" (em_rst), "i" (mp_ne_set) : "eax");
313 
314 	/* identify CPU via cpuid and store the decoded info into gd->arch */
315 	if (has_cpuid()) {
316 		struct cpu_device_id cpu;
317 		struct cpuinfo_x86 c;
318 
319 		identify_cpu(&cpu);
320 		get_fms(&c, cpu.device);
321 		gd->arch.x86 = c.x86;
322 		gd->arch.x86_vendor = cpu.vendor;
323 		gd->arch.x86_model = c.x86_model;
324 		gd->arch.x86_mask = c.x86_mask;
325 		gd->arch.x86_device = cpu.device;
326 
327 		gd->arch.has_mtrr = has_mtrr();
328 	}
329 
330 	return 0;
331 }
332 
333 void x86_enable_caches(void)
334 {
335 	unsigned long cr0;
336 
337 	cr0 = read_cr0();
338 	cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
339 	write_cr0(cr0);
340 	wbinvd();
341 }
342 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
343 
344 void x86_disable_caches(void)
345 {
346 	unsigned long cr0;
347 
348 	cr0 = read_cr0();
349 	cr0 |= X86_CR0_NW | X86_CR0_CD;
350 	wbinvd();
351 	write_cr0(cr0);
352 	wbinvd();
353 }
354 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
355 
356 int x86_init_cache(void)
357 {
358 	enable_caches();
359 
360 	return 0;
361 }
362 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
363 
364 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
365 {
366 	printf("resetting ...\n");
367 
368 	/* wait 50 ms */
369 	udelay(50000);
370 	disable_interrupts();
371 	reset_cpu(0);
372 
373 	/*NOTREACHED*/
374 	return 0;
375 }
376 
377 void  flush_cache(unsigned long dummy1, unsigned long dummy2)
378 {
379 	asm("wbinvd\n");
380 }
381 
382 void __attribute__ ((regparm(0))) generate_gpf(void);
383 
384 /* segment 0x70 is an arbitrary segment which does not exist */
385 asm(".globl generate_gpf\n"
386 	".hidden generate_gpf\n"
387 	".type generate_gpf, @function\n"
388 	"generate_gpf:\n"
389 	"ljmp   $0x70, $0x47114711\n");
390 
391 __weak void reset_cpu(ulong addr)
392 {
393 	printf("Resetting using x86 Triple Fault\n");
394 	set_vector(13, generate_gpf);	/* general protection fault handler */
395 	set_vector(8, generate_gpf);	/* double fault handler */
396 	generate_gpf();			/* start the show */
397 }
398 
399 int dcache_status(void)
400 {
401 	return !(read_cr0() & 0x40000000);
402 }
403 
404 /* Define these functions to allow ehch-hcd to function */
405 void flush_dcache_range(unsigned long start, unsigned long stop)
406 {
407 }
408 
409 void invalidate_dcache_range(unsigned long start, unsigned long stop)
410 {
411 }
412 
413 void dcache_enable(void)
414 {
415 	enable_caches();
416 }
417 
418 void dcache_disable(void)
419 {
420 	disable_caches();
421 }
422 
423 void icache_enable(void)
424 {
425 }
426 
427 void icache_disable(void)
428 {
429 }
430 
431 int icache_status(void)
432 {
433 	return 1;
434 }
435 
436 void cpu_enable_paging_pae(ulong cr3)
437 {
438 	__asm__ __volatile__(
439 		/* Load the page table address */
440 		"movl	%0, %%cr3\n"
441 		/* Enable pae */
442 		"movl	%%cr4, %%eax\n"
443 		"orl	$0x00000020, %%eax\n"
444 		"movl	%%eax, %%cr4\n"
445 		/* Enable paging */
446 		"movl	%%cr0, %%eax\n"
447 		"orl	$0x80000000, %%eax\n"
448 		"movl	%%eax, %%cr0\n"
449 		:
450 		: "r" (cr3)
451 		: "eax");
452 }
453 
454 void cpu_disable_paging_pae(void)
455 {
456 	/* Turn off paging */
457 	__asm__ __volatile__ (
458 		/* Disable paging */
459 		"movl	%%cr0, %%eax\n"
460 		"andl	$0x7fffffff, %%eax\n"
461 		"movl	%%eax, %%cr0\n"
462 		/* Disable pae */
463 		"movl	%%cr4, %%eax\n"
464 		"andl	$0xffffffdf, %%eax\n"
465 		"movl	%%eax, %%cr4\n"
466 		:
467 		:
468 		: "eax");
469 }
470 
471 static bool can_detect_long_mode(void)
472 {
473 	return cpuid_eax(0x80000000) > 0x80000000UL;
474 }
475 
476 static bool has_long_mode(void)
477 {
478 	return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
479 }
480 
481 int cpu_has_64bit(void)
482 {
483 	return has_cpuid() && can_detect_long_mode() &&
484 		has_long_mode();
485 }
486 
487 const char *cpu_vendor_name(int vendor)
488 {
489 	const char *name;
490 	name = "<invalid cpu vendor>";
491 	if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
492 	    (x86_vendor_name[vendor] != 0))
493 		name = x86_vendor_name[vendor];
494 
495 	return name;
496 }
497 
498 char *cpu_get_name(char *name)
499 {
500 	unsigned int *name_as_ints = (unsigned int *)name;
501 	struct cpuid_result regs;
502 	char *ptr;
503 	int i;
504 
505 	/* This bit adds up to 48 bytes */
506 	for (i = 0; i < 3; i++) {
507 		regs = cpuid(0x80000002 + i);
508 		name_as_ints[i * 4 + 0] = regs.eax;
509 		name_as_ints[i * 4 + 1] = regs.ebx;
510 		name_as_ints[i * 4 + 2] = regs.ecx;
511 		name_as_ints[i * 4 + 3] = regs.edx;
512 	}
513 	name[CPU_MAX_NAME_LEN - 1] = '\0';
514 
515 	/* Skip leading spaces. */
516 	ptr = name;
517 	while (*ptr == ' ')
518 		ptr++;
519 
520 	return ptr;
521 }
522 
523 int default_print_cpuinfo(void)
524 {
525 	printf("CPU: %s, vendor %s, device %xh\n",
526 	       cpu_has_64bit() ? "x86_64" : "x86",
527 	       cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
528 
529 	return 0;
530 }
531 
532 #define PAGETABLE_SIZE		(6 * 4096)
533 
534 /**
535  * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
536  *
537  * @pgtable: Pointer to a 24iKB block of memory
538  */
539 static void build_pagetable(uint32_t *pgtable)
540 {
541 	uint i;
542 
543 	memset(pgtable, '\0', PAGETABLE_SIZE);
544 
545 	/* Level 4 needs a single entry */
546 	pgtable[0] = (uint32_t)&pgtable[1024] + 7;
547 
548 	/* Level 3 has one 64-bit entry for each GiB of memory */
549 	for (i = 0; i < 4; i++) {
550 		pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
551 							0x1000 * i + 7;
552 	}
553 
554 	/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
555 	for (i = 0; i < 2048; i++)
556 		pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
557 }
558 
559 int cpu_jump_to_64bit(ulong setup_base, ulong target)
560 {
561 	uint32_t *pgtable;
562 
563 	pgtable = memalign(4096, PAGETABLE_SIZE);
564 	if (!pgtable)
565 		return -ENOMEM;
566 
567 	build_pagetable(pgtable);
568 	cpu_call64((ulong)pgtable, setup_base, target);
569 	free(pgtable);
570 
571 	return -EFAULT;
572 }
573 
574 void show_boot_progress(int val)
575 {
576 #if MIN_PORT80_KCLOCKS_DELAY
577 	/*
578 	 * Scale the time counter reading to avoid using 64 bit arithmetics.
579 	 * Can't use get_timer() here becuase it could be not yet
580 	 * initialized or even implemented.
581 	 */
582 	if (!gd->arch.tsc_prev) {
583 		gd->arch.tsc_base_kclocks = rdtsc() / 1000;
584 		gd->arch.tsc_prev = 0;
585 	} else {
586 		uint32_t now;
587 
588 		do {
589 			now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
590 		} while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
591 		gd->arch.tsc_prev = now;
592 	}
593 #endif
594 	outb(val, POST_PORT);
595 }
596