xref: /openbmc/u-boot/arch/x86/cpu/cpu.c (revision 9e374e7b) 
1 /*
2  * (C) Copyright 2008-2011
3  * Graeme Russ, <graeme.russ@gmail.com>
4  *
5  * (C) Copyright 2002
6  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
7  *
8  * (C) Copyright 2002
9  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10  * Marius Groeger <mgroeger@sysgo.de>
11  *
12  * (C) Copyright 2002
13  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14  * Alex Zuepke <azu@sysgo.de>
15  *
16  * Part of this file is adapted from coreboot
17  * src/arch/x86/lib/cpu.c
18  *
19  * SPDX-License-Identifier:	GPL-2.0+
20  */
21 
22 #include <common.h>
23 #include <command.h>
24 #include <errno.h>
25 #include <malloc.h>
26 #include <asm/control_regs.h>
27 #include <asm/cpu.h>
28 #include <asm/post.h>
29 #include <asm/processor.h>
30 #include <asm/processor-flags.h>
31 #include <asm/interrupt.h>
32 #include <linux/compiler.h>
33 
34 DECLARE_GLOBAL_DATA_PTR;
35 
36 /*
37  * Constructor for a conventional segment GDT (or LDT) entry
38  * This is a macro so it can be used in initialisers
39  */
40 #define GDT_ENTRY(flags, base, limit)			\
41 	((((base)  & 0xff000000ULL) << (56-24)) |	\
42 	 (((flags) & 0x0000f0ffULL) << 40) |		\
43 	 (((limit) & 0x000f0000ULL) << (48-16)) |	\
44 	 (((base)  & 0x00ffffffULL) << 16) |		\
45 	 (((limit) & 0x0000ffffULL)))
46 
47 struct gdt_ptr {
48 	u16 len;
49 	u32 ptr;
50 } __packed;
51 
52 struct cpu_device_id {
53 	unsigned vendor;
54 	unsigned device;
55 };
56 
57 struct cpuinfo_x86 {
58 	uint8_t x86;            /* CPU family */
59 	uint8_t x86_vendor;     /* CPU vendor */
60 	uint8_t x86_model;
61 	uint8_t x86_mask;
62 };
63 
64 /*
65  * List of cpu vendor strings along with their normalized
66  * id values.
67  */
68 static struct {
69 	int vendor;
70 	const char *name;
71 } x86_vendors[] = {
72 	{ X86_VENDOR_INTEL,     "GenuineIntel", },
73 	{ X86_VENDOR_CYRIX,     "CyrixInstead", },
74 	{ X86_VENDOR_AMD,       "AuthenticAMD", },
75 	{ X86_VENDOR_UMC,       "UMC UMC UMC ", },
76 	{ X86_VENDOR_NEXGEN,    "NexGenDriven", },
77 	{ X86_VENDOR_CENTAUR,   "CentaurHauls", },
78 	{ X86_VENDOR_RISE,      "RiseRiseRise", },
79 	{ X86_VENDOR_TRANSMETA, "GenuineTMx86", },
80 	{ X86_VENDOR_TRANSMETA, "TransmetaCPU", },
81 	{ X86_VENDOR_NSC,       "Geode by NSC", },
82 	{ X86_VENDOR_SIS,       "SiS SiS SiS ", },
83 };
84 
85 static const char *const x86_vendor_name[] = {
86 	[X86_VENDOR_INTEL]     = "Intel",
87 	[X86_VENDOR_CYRIX]     = "Cyrix",
88 	[X86_VENDOR_AMD]       = "AMD",
89 	[X86_VENDOR_UMC]       = "UMC",
90 	[X86_VENDOR_NEXGEN]    = "NexGen",
91 	[X86_VENDOR_CENTAUR]   = "Centaur",
92 	[X86_VENDOR_RISE]      = "Rise",
93 	[X86_VENDOR_TRANSMETA] = "Transmeta",
94 	[X86_VENDOR_NSC]       = "NSC",
95 	[X86_VENDOR_SIS]       = "SiS",
96 };
97 
98 static void load_ds(u32 segment)
99 {
100 	asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
101 }
102 
103 static void load_es(u32 segment)
104 {
105 	asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
106 }
107 
108 static void load_fs(u32 segment)
109 {
110 	asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
111 }
112 
113 static void load_gs(u32 segment)
114 {
115 	asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
116 }
117 
118 static void load_ss(u32 segment)
119 {
120 	asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
121 }
122 
123 static void load_gdt(const u64 *boot_gdt, u16 num_entries)
124 {
125 	struct gdt_ptr gdt;
126 
127 	gdt.len = (num_entries * 8) - 1;
128 	gdt.ptr = (u32)boot_gdt;
129 
130 	asm volatile("lgdtl %0\n" : : "m" (gdt));
131 }
132 
133 void setup_gdt(gd_t *id, u64 *gdt_addr)
134 {
135 	/* CS: code, read/execute, 4 GB, base 0 */
136 	gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
137 
138 	/* DS: data, read/write, 4 GB, base 0 */
139 	gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
140 
141 	/* FS: data, read/write, 4 GB, base (Global Data Pointer) */
142 	id->arch.gd_addr = id;
143 	gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
144 		     (ulong)&id->arch.gd_addr, 0xfffff);
145 
146 	/* 16-bit CS: code, read/execute, 64 kB, base 0 */
147 	gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff);
148 
149 	/* 16-bit DS: data, read/write, 64 kB, base 0 */
150 	gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff);
151 
152 	load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
153 	load_ds(X86_GDT_ENTRY_32BIT_DS);
154 	load_es(X86_GDT_ENTRY_32BIT_DS);
155 	load_gs(X86_GDT_ENTRY_32BIT_DS);
156 	load_ss(X86_GDT_ENTRY_32BIT_DS);
157 	load_fs(X86_GDT_ENTRY_32BIT_FS);
158 }
159 
160 int __weak x86_cleanup_before_linux(void)
161 {
162 #ifdef CONFIG_BOOTSTAGE_STASH
163 	bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH,
164 			CONFIG_BOOTSTAGE_STASH_SIZE);
165 #endif
166 
167 	return 0;
168 }
169 
170 /*
171  * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
172  * by the fact that they preserve the flags across the division of 5/2.
173  * PII and PPro exhibit this behavior too, but they have cpuid available.
174  */
175 
176 /*
177  * Perform the Cyrix 5/2 test. A Cyrix won't change
178  * the flags, while other 486 chips will.
179  */
180 static inline int test_cyrix_52div(void)
181 {
182 	unsigned int test;
183 
184 	__asm__ __volatile__(
185 	     "sahf\n\t"		/* clear flags (%eax = 0x0005) */
186 	     "div %b2\n\t"	/* divide 5 by 2 */
187 	     "lahf"		/* store flags into %ah */
188 	     : "=a" (test)
189 	     : "0" (5), "q" (2)
190 	     : "cc");
191 
192 	/* AH is 0x02 on Cyrix after the divide.. */
193 	return (unsigned char) (test >> 8) == 0x02;
194 }
195 
196 /*
197  *	Detect a NexGen CPU running without BIOS hypercode new enough
198  *	to have CPUID. (Thanks to Herbert Oppmann)
199  */
200 
201 static int deep_magic_nexgen_probe(void)
202 {
203 	int ret;
204 
205 	__asm__ __volatile__ (
206 		"	movw	$0x5555, %%ax\n"
207 		"	xorw	%%dx,%%dx\n"
208 		"	movw	$2, %%cx\n"
209 		"	divw	%%cx\n"
210 		"	movl	$0, %%eax\n"
211 		"	jnz	1f\n"
212 		"	movl	$1, %%eax\n"
213 		"1:\n"
214 		: "=a" (ret) : : "cx", "dx");
215 	return  ret;
216 }
217 
218 static bool has_cpuid(void)
219 {
220 	return flag_is_changeable_p(X86_EFLAGS_ID);
221 }
222 
223 static int build_vendor_name(char *vendor_name)
224 {
225 	struct cpuid_result result;
226 	result = cpuid(0x00000000);
227 	unsigned int *name_as_ints = (unsigned int *)vendor_name;
228 
229 	name_as_ints[0] = result.ebx;
230 	name_as_ints[1] = result.edx;
231 	name_as_ints[2] = result.ecx;
232 
233 	return result.eax;
234 }
235 
236 static void identify_cpu(struct cpu_device_id *cpu)
237 {
238 	char vendor_name[16];
239 	int i;
240 
241 	vendor_name[0] = '\0'; /* Unset */
242 	cpu->device = 0; /* fix gcc 4.4.4 warning */
243 
244 	/* Find the id and vendor_name */
245 	if (!has_cpuid()) {
246 		/* Its a 486 if we can modify the AC flag */
247 		if (flag_is_changeable_p(X86_EFLAGS_AC))
248 			cpu->device = 0x00000400; /* 486 */
249 		else
250 			cpu->device = 0x00000300; /* 386 */
251 		if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
252 			memcpy(vendor_name, "CyrixInstead", 13);
253 			/* If we ever care we can enable cpuid here */
254 		}
255 		/* Detect NexGen with old hypercode */
256 		else if (deep_magic_nexgen_probe())
257 			memcpy(vendor_name, "NexGenDriven", 13);
258 	}
259 	if (has_cpuid()) {
260 		int  cpuid_level;
261 
262 		cpuid_level = build_vendor_name(vendor_name);
263 		vendor_name[12] = '\0';
264 
265 		/* Intel-defined flags: level 0x00000001 */
266 		if (cpuid_level >= 0x00000001) {
267 			cpu->device = cpuid_eax(0x00000001);
268 		} else {
269 			/* Have CPUID level 0 only unheard of */
270 			cpu->device = 0x00000400;
271 		}
272 	}
273 	cpu->vendor = X86_VENDOR_UNKNOWN;
274 	for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
275 		if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
276 			cpu->vendor = x86_vendors[i].vendor;
277 			break;
278 		}
279 	}
280 }
281 
282 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
283 {
284 	c->x86 = (tfms >> 8) & 0xf;
285 	c->x86_model = (tfms >> 4) & 0xf;
286 	c->x86_mask = tfms & 0xf;
287 	if (c->x86 == 0xf)
288 		c->x86 += (tfms >> 20) & 0xff;
289 	if (c->x86 >= 0x6)
290 		c->x86_model += ((tfms >> 16) & 0xF) << 4;
291 }
292 
293 int x86_cpu_init_f(void)
294 {
295 	const u32 em_rst = ~X86_CR0_EM;
296 	const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
297 
298 	/* initialize FPU, reset EM, set MP and NE */
299 	asm ("fninit\n" \
300 	     "movl %%cr0, %%eax\n" \
301 	     "andl %0, %%eax\n" \
302 	     "orl  %1, %%eax\n" \
303 	     "movl %%eax, %%cr0\n" \
304 	     : : "i" (em_rst), "i" (mp_ne_set) : "eax");
305 
306 	/* identify CPU via cpuid and store the decoded info into gd->arch */
307 	if (has_cpuid()) {
308 		struct cpu_device_id cpu;
309 		struct cpuinfo_x86 c;
310 
311 		identify_cpu(&cpu);
312 		get_fms(&c, cpu.device);
313 		gd->arch.x86 = c.x86;
314 		gd->arch.x86_vendor = cpu.vendor;
315 		gd->arch.x86_model = c.x86_model;
316 		gd->arch.x86_mask = c.x86_mask;
317 		gd->arch.x86_device = cpu.device;
318 	}
319 
320 	return 0;
321 }
322 
323 int x86_cpu_init_r(void)
324 {
325 	/* Initialize core interrupt and exception functionality of CPU */
326 	cpu_init_interrupts();
327 	return 0;
328 }
329 int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
330 
331 void x86_enable_caches(void)
332 {
333 	unsigned long cr0;
334 
335 	cr0 = read_cr0();
336 	cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
337 	write_cr0(cr0);
338 	wbinvd();
339 }
340 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
341 
342 void x86_disable_caches(void)
343 {
344 	unsigned long cr0;
345 
346 	cr0 = read_cr0();
347 	cr0 |= X86_CR0_NW | X86_CR0_CD;
348 	wbinvd();
349 	write_cr0(cr0);
350 	wbinvd();
351 }
352 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
353 
354 int x86_init_cache(void)
355 {
356 	enable_caches();
357 
358 	return 0;
359 }
360 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
361 
362 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
363 {
364 	printf("resetting ...\n");
365 
366 	/* wait 50 ms */
367 	udelay(50000);
368 	disable_interrupts();
369 	reset_cpu(0);
370 
371 	/*NOTREACHED*/
372 	return 0;
373 }
374 
375 void  flush_cache(unsigned long dummy1, unsigned long dummy2)
376 {
377 	asm("wbinvd\n");
378 }
379 
380 void __attribute__ ((regparm(0))) generate_gpf(void);
381 
382 /* segment 0x70 is an arbitrary segment which does not exist */
383 asm(".globl generate_gpf\n"
384 	".hidden generate_gpf\n"
385 	".type generate_gpf, @function\n"
386 	"generate_gpf:\n"
387 	"ljmp   $0x70, $0x47114711\n");
388 
389 __weak void reset_cpu(ulong addr)
390 {
391 	printf("Resetting using x86 Triple Fault\n");
392 	set_vector(13, generate_gpf);	/* general protection fault handler */
393 	set_vector(8, generate_gpf);	/* double fault handler */
394 	generate_gpf();			/* start the show */
395 }
396 
397 int dcache_status(void)
398 {
399 	return !(read_cr0() & 0x40000000);
400 }
401 
402 /* Define these functions to allow ehch-hcd to function */
403 void flush_dcache_range(unsigned long start, unsigned long stop)
404 {
405 }
406 
407 void invalidate_dcache_range(unsigned long start, unsigned long stop)
408 {
409 }
410 
411 void dcache_enable(void)
412 {
413 	enable_caches();
414 }
415 
416 void dcache_disable(void)
417 {
418 	disable_caches();
419 }
420 
421 void icache_enable(void)
422 {
423 }
424 
425 void icache_disable(void)
426 {
427 }
428 
429 int icache_status(void)
430 {
431 	return 1;
432 }
433 
434 void cpu_enable_paging_pae(ulong cr3)
435 {
436 	__asm__ __volatile__(
437 		/* Load the page table address */
438 		"movl	%0, %%cr3\n"
439 		/* Enable pae */
440 		"movl	%%cr4, %%eax\n"
441 		"orl	$0x00000020, %%eax\n"
442 		"movl	%%eax, %%cr4\n"
443 		/* Enable paging */
444 		"movl	%%cr0, %%eax\n"
445 		"orl	$0x80000000, %%eax\n"
446 		"movl	%%eax, %%cr0\n"
447 		:
448 		: "r" (cr3)
449 		: "eax");
450 }
451 
452 void cpu_disable_paging_pae(void)
453 {
454 	/* Turn off paging */
455 	__asm__ __volatile__ (
456 		/* Disable paging */
457 		"movl	%%cr0, %%eax\n"
458 		"andl	$0x7fffffff, %%eax\n"
459 		"movl	%%eax, %%cr0\n"
460 		/* Disable pae */
461 		"movl	%%cr4, %%eax\n"
462 		"andl	$0xffffffdf, %%eax\n"
463 		"movl	%%eax, %%cr4\n"
464 		:
465 		:
466 		: "eax");
467 }
468 
469 static bool can_detect_long_mode(void)
470 {
471 	return cpuid_eax(0x80000000) > 0x80000000UL;
472 }
473 
474 static bool has_long_mode(void)
475 {
476 	return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
477 }
478 
479 int cpu_has_64bit(void)
480 {
481 	return has_cpuid() && can_detect_long_mode() &&
482 		has_long_mode();
483 }
484 
485 const char *cpu_vendor_name(int vendor)
486 {
487 	const char *name;
488 	name = "<invalid cpu vendor>";
489 	if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
490 	    (x86_vendor_name[vendor] != 0))
491 		name = x86_vendor_name[vendor];
492 
493 	return name;
494 }
495 
496 char *cpu_get_name(char *name)
497 {
498 	unsigned int *name_as_ints = (unsigned int *)name;
499 	struct cpuid_result regs;
500 	char *ptr;
501 	int i;
502 
503 	/* This bit adds up to 48 bytes */
504 	for (i = 0; i < 3; i++) {
505 		regs = cpuid(0x80000002 + i);
506 		name_as_ints[i * 4 + 0] = regs.eax;
507 		name_as_ints[i * 4 + 1] = regs.ebx;
508 		name_as_ints[i * 4 + 2] = regs.ecx;
509 		name_as_ints[i * 4 + 3] = regs.edx;
510 	}
511 	name[CPU_MAX_NAME_LEN - 1] = '\0';
512 
513 	/* Skip leading spaces. */
514 	ptr = name;
515 	while (*ptr == ' ')
516 		ptr++;
517 
518 	return ptr;
519 }
520 
521 int default_print_cpuinfo(void)
522 {
523 	printf("CPU: %s, vendor %s, device %xh\n",
524 	       cpu_has_64bit() ? "x86_64" : "x86",
525 	       cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
526 
527 	return 0;
528 }
529 
530 #define PAGETABLE_SIZE		(6 * 4096)
531 
532 /**
533  * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
534  *
535  * @pgtable: Pointer to a 24iKB block of memory
536  */
537 static void build_pagetable(uint32_t *pgtable)
538 {
539 	uint i;
540 
541 	memset(pgtable, '\0', PAGETABLE_SIZE);
542 
543 	/* Level 4 needs a single entry */
544 	pgtable[0] = (uint32_t)&pgtable[1024] + 7;
545 
546 	/* Level 3 has one 64-bit entry for each GiB of memory */
547 	for (i = 0; i < 4; i++) {
548 		pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
549 							0x1000 * i + 7;
550 	}
551 
552 	/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
553 	for (i = 0; i < 2048; i++)
554 		pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
555 }
556 
557 int cpu_jump_to_64bit(ulong setup_base, ulong target)
558 {
559 	uint32_t *pgtable;
560 
561 	pgtable = memalign(4096, PAGETABLE_SIZE);
562 	if (!pgtable)
563 		return -ENOMEM;
564 
565 	build_pagetable(pgtable);
566 	cpu_call64((ulong)pgtable, setup_base, target);
567 	free(pgtable);
568 
569 	return -EFAULT;
570 }
571 
572 void show_boot_progress(int val)
573 {
574 #if MIN_PORT80_KCLOCKS_DELAY
575 	/*
576 	 * Scale the time counter reading to avoid using 64 bit arithmetics.
577 	 * Can't use get_timer() here becuase it could be not yet
578 	 * initialized or even implemented.
579 	 */
580 	if (!gd->arch.tsc_prev) {
581 		gd->arch.tsc_base_kclocks = rdtsc() / 1000;
582 		gd->arch.tsc_prev = 0;
583 	} else {
584 		uint32_t now;
585 
586 		do {
587 			now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
588 		} while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
589 		gd->arch.tsc_prev = now;
590 	}
591 #endif
592 	outb(val, POST_PORT);
593 }
594