1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * Part of this file is adapted from coreboot 17 * src/arch/x86/lib/cpu.c 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22 #include <common.h> 23 #include <command.h> 24 #include <dm.h> 25 #include <errno.h> 26 #include <malloc.h> 27 #include <asm/control_regs.h> 28 #include <asm/cpu.h> 29 #include <asm/lapic.h> 30 #include <asm/mp.h> 31 #include <asm/msr.h> 32 #include <asm/mtrr.h> 33 #include <asm/post.h> 34 #include <asm/processor.h> 35 #include <asm/processor-flags.h> 36 #include <asm/interrupt.h> 37 #include <asm/tables.h> 38 #include <linux/compiler.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 /* 43 * Constructor for a conventional segment GDT (or LDT) entry 44 * This is a macro so it can be used in initialisers 45 */ 46 #define GDT_ENTRY(flags, base, limit) \ 47 ((((base) & 0xff000000ULL) << (56-24)) | \ 48 (((flags) & 0x0000f0ffULL) << 40) | \ 49 (((limit) & 0x000f0000ULL) << (48-16)) | \ 50 (((base) & 0x00ffffffULL) << 16) | \ 51 (((limit) & 0x0000ffffULL))) 52 53 struct gdt_ptr { 54 u16 len; 55 u32 ptr; 56 } __packed; 57 58 struct cpu_device_id { 59 unsigned vendor; 60 unsigned device; 61 }; 62 63 struct cpuinfo_x86 { 64 uint8_t x86; /* CPU family */ 65 uint8_t x86_vendor; /* CPU vendor */ 66 uint8_t x86_model; 67 uint8_t x86_mask; 68 }; 69 70 /* 71 * List of cpu vendor strings along with their normalized 72 * id values. 73 */ 74 static struct { 75 int vendor; 76 const char *name; 77 } x86_vendors[] = { 78 { X86_VENDOR_INTEL, "GenuineIntel", }, 79 { X86_VENDOR_CYRIX, "CyrixInstead", }, 80 { X86_VENDOR_AMD, "AuthenticAMD", }, 81 { X86_VENDOR_UMC, "UMC UMC UMC ", }, 82 { X86_VENDOR_NEXGEN, "NexGenDriven", }, 83 { X86_VENDOR_CENTAUR, "CentaurHauls", }, 84 { X86_VENDOR_RISE, "RiseRiseRise", }, 85 { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, 86 { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, 87 { X86_VENDOR_NSC, "Geode by NSC", }, 88 { X86_VENDOR_SIS, "SiS SiS SiS ", }, 89 }; 90 91 static const char *const x86_vendor_name[] = { 92 [X86_VENDOR_INTEL] = "Intel", 93 [X86_VENDOR_CYRIX] = "Cyrix", 94 [X86_VENDOR_AMD] = "AMD", 95 [X86_VENDOR_UMC] = "UMC", 96 [X86_VENDOR_NEXGEN] = "NexGen", 97 [X86_VENDOR_CENTAUR] = "Centaur", 98 [X86_VENDOR_RISE] = "Rise", 99 [X86_VENDOR_TRANSMETA] = "Transmeta", 100 [X86_VENDOR_NSC] = "NSC", 101 [X86_VENDOR_SIS] = "SiS", 102 }; 103 104 static void load_ds(u32 segment) 105 { 106 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 107 } 108 109 static void load_es(u32 segment) 110 { 111 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 112 } 113 114 static void load_fs(u32 segment) 115 { 116 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 117 } 118 119 static void load_gs(u32 segment) 120 { 121 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 122 } 123 124 static void load_ss(u32 segment) 125 { 126 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 127 } 128 129 static void load_gdt(const u64 *boot_gdt, u16 num_entries) 130 { 131 struct gdt_ptr gdt; 132 133 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; 134 gdt.ptr = (u32)boot_gdt; 135 136 asm volatile("lgdtl %0\n" : : "m" (gdt)); 137 } 138 139 void setup_gdt(gd_t *id, u64 *gdt_addr) 140 { 141 id->arch.gdt = gdt_addr; 142 /* CS: code, read/execute, 4 GB, base 0 */ 143 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); 144 145 /* DS: data, read/write, 4 GB, base 0 */ 146 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); 147 148 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ 149 id->arch.gd_addr = id; 150 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, 151 (ulong)&id->arch.gd_addr, 0xfffff); 152 153 /* 16-bit CS: code, read/execute, 64 kB, base 0 */ 154 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); 155 156 /* 16-bit DS: data, read/write, 64 kB, base 0 */ 157 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); 158 159 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); 160 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); 161 162 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); 163 load_ds(X86_GDT_ENTRY_32BIT_DS); 164 load_es(X86_GDT_ENTRY_32BIT_DS); 165 load_gs(X86_GDT_ENTRY_32BIT_DS); 166 load_ss(X86_GDT_ENTRY_32BIT_DS); 167 load_fs(X86_GDT_ENTRY_32BIT_FS); 168 } 169 170 #ifdef CONFIG_HAVE_FSP 171 /* 172 * Setup FSP execution environment GDT 173 * 174 * Per Intel FSP external architecture specification, before calling any FSP 175 * APIs, we need make sure the system is in flat 32-bit mode and both the code 176 * and data selectors should have full 4GB access range. Here we reuse the one 177 * we used in arch/x86/cpu/start16.S, and reload the segement registers. 178 */ 179 void setup_fsp_gdt(void) 180 { 181 load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4); 182 load_ds(X86_GDT_ENTRY_32BIT_DS); 183 load_ss(X86_GDT_ENTRY_32BIT_DS); 184 load_es(X86_GDT_ENTRY_32BIT_DS); 185 load_fs(X86_GDT_ENTRY_32BIT_DS); 186 load_gs(X86_GDT_ENTRY_32BIT_DS); 187 } 188 #endif 189 190 int __weak x86_cleanup_before_linux(void) 191 { 192 #ifdef CONFIG_BOOTSTAGE_STASH 193 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, 194 CONFIG_BOOTSTAGE_STASH_SIZE); 195 #endif 196 197 return 0; 198 } 199 200 /* 201 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected 202 * by the fact that they preserve the flags across the division of 5/2. 203 * PII and PPro exhibit this behavior too, but they have cpuid available. 204 */ 205 206 /* 207 * Perform the Cyrix 5/2 test. A Cyrix won't change 208 * the flags, while other 486 chips will. 209 */ 210 static inline int test_cyrix_52div(void) 211 { 212 unsigned int test; 213 214 __asm__ __volatile__( 215 "sahf\n\t" /* clear flags (%eax = 0x0005) */ 216 "div %b2\n\t" /* divide 5 by 2 */ 217 "lahf" /* store flags into %ah */ 218 : "=a" (test) 219 : "0" (5), "q" (2) 220 : "cc"); 221 222 /* AH is 0x02 on Cyrix after the divide.. */ 223 return (unsigned char) (test >> 8) == 0x02; 224 } 225 226 /* 227 * Detect a NexGen CPU running without BIOS hypercode new enough 228 * to have CPUID. (Thanks to Herbert Oppmann) 229 */ 230 231 static int deep_magic_nexgen_probe(void) 232 { 233 int ret; 234 235 __asm__ __volatile__ ( 236 " movw $0x5555, %%ax\n" 237 " xorw %%dx,%%dx\n" 238 " movw $2, %%cx\n" 239 " divw %%cx\n" 240 " movl $0, %%eax\n" 241 " jnz 1f\n" 242 " movl $1, %%eax\n" 243 "1:\n" 244 : "=a" (ret) : : "cx", "dx"); 245 return ret; 246 } 247 248 static bool has_cpuid(void) 249 { 250 return flag_is_changeable_p(X86_EFLAGS_ID); 251 } 252 253 static bool has_mtrr(void) 254 { 255 return cpuid_edx(0x00000001) & (1 << 12) ? true : false; 256 } 257 258 static int build_vendor_name(char *vendor_name) 259 { 260 struct cpuid_result result; 261 result = cpuid(0x00000000); 262 unsigned int *name_as_ints = (unsigned int *)vendor_name; 263 264 name_as_ints[0] = result.ebx; 265 name_as_ints[1] = result.edx; 266 name_as_ints[2] = result.ecx; 267 268 return result.eax; 269 } 270 271 static void identify_cpu(struct cpu_device_id *cpu) 272 { 273 char vendor_name[16]; 274 int i; 275 276 vendor_name[0] = '\0'; /* Unset */ 277 cpu->device = 0; /* fix gcc 4.4.4 warning */ 278 279 /* Find the id and vendor_name */ 280 if (!has_cpuid()) { 281 /* Its a 486 if we can modify the AC flag */ 282 if (flag_is_changeable_p(X86_EFLAGS_AC)) 283 cpu->device = 0x00000400; /* 486 */ 284 else 285 cpu->device = 0x00000300; /* 386 */ 286 if ((cpu->device == 0x00000400) && test_cyrix_52div()) { 287 memcpy(vendor_name, "CyrixInstead", 13); 288 /* If we ever care we can enable cpuid here */ 289 } 290 /* Detect NexGen with old hypercode */ 291 else if (deep_magic_nexgen_probe()) 292 memcpy(vendor_name, "NexGenDriven", 13); 293 } 294 if (has_cpuid()) { 295 int cpuid_level; 296 297 cpuid_level = build_vendor_name(vendor_name); 298 vendor_name[12] = '\0'; 299 300 /* Intel-defined flags: level 0x00000001 */ 301 if (cpuid_level >= 0x00000001) { 302 cpu->device = cpuid_eax(0x00000001); 303 } else { 304 /* Have CPUID level 0 only unheard of */ 305 cpu->device = 0x00000400; 306 } 307 } 308 cpu->vendor = X86_VENDOR_UNKNOWN; 309 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { 310 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { 311 cpu->vendor = x86_vendors[i].vendor; 312 break; 313 } 314 } 315 } 316 317 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) 318 { 319 c->x86 = (tfms >> 8) & 0xf; 320 c->x86_model = (tfms >> 4) & 0xf; 321 c->x86_mask = tfms & 0xf; 322 if (c->x86 == 0xf) 323 c->x86 += (tfms >> 20) & 0xff; 324 if (c->x86 >= 0x6) 325 c->x86_model += ((tfms >> 16) & 0xF) << 4; 326 } 327 328 int x86_cpu_init_f(void) 329 { 330 const u32 em_rst = ~X86_CR0_EM; 331 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; 332 333 /* initialize FPU, reset EM, set MP and NE */ 334 asm ("fninit\n" \ 335 "movl %%cr0, %%eax\n" \ 336 "andl %0, %%eax\n" \ 337 "orl %1, %%eax\n" \ 338 "movl %%eax, %%cr0\n" \ 339 : : "i" (em_rst), "i" (mp_ne_set) : "eax"); 340 341 /* identify CPU via cpuid and store the decoded info into gd->arch */ 342 if (has_cpuid()) { 343 struct cpu_device_id cpu; 344 struct cpuinfo_x86 c; 345 346 identify_cpu(&cpu); 347 get_fms(&c, cpu.device); 348 gd->arch.x86 = c.x86; 349 gd->arch.x86_vendor = cpu.vendor; 350 gd->arch.x86_model = c.x86_model; 351 gd->arch.x86_mask = c.x86_mask; 352 gd->arch.x86_device = cpu.device; 353 354 gd->arch.has_mtrr = has_mtrr(); 355 } 356 /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */ 357 gd->pci_ram_top = 0x80000000U; 358 359 /* Configure fixed range MTRRs for some legacy regions */ 360 if (gd->arch.has_mtrr) { 361 u64 mtrr_cap; 362 363 mtrr_cap = native_read_msr(MTRR_CAP_MSR); 364 if (mtrr_cap & MTRR_CAP_FIX) { 365 /* Mark the VGA RAM area as uncacheable */ 366 native_write_msr(MTRR_FIX_16K_A0000_MSR, 367 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE), 368 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); 369 370 /* 371 * Mark the PCI ROM area as cacheable to improve ROM 372 * execution performance. 373 */ 374 native_write_msr(MTRR_FIX_4K_C0000_MSR, 375 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 376 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 377 native_write_msr(MTRR_FIX_4K_C8000_MSR, 378 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 379 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 380 native_write_msr(MTRR_FIX_4K_D0000_MSR, 381 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 382 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 383 native_write_msr(MTRR_FIX_4K_D8000_MSR, 384 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 385 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 386 387 /* Enable the fixed range MTRRs */ 388 msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); 389 } 390 } 391 392 return 0; 393 } 394 395 void x86_enable_caches(void) 396 { 397 unsigned long cr0; 398 399 cr0 = read_cr0(); 400 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); 401 write_cr0(cr0); 402 wbinvd(); 403 } 404 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); 405 406 void x86_disable_caches(void) 407 { 408 unsigned long cr0; 409 410 cr0 = read_cr0(); 411 cr0 |= X86_CR0_NW | X86_CR0_CD; 412 wbinvd(); 413 write_cr0(cr0); 414 wbinvd(); 415 } 416 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); 417 418 int x86_init_cache(void) 419 { 420 enable_caches(); 421 422 return 0; 423 } 424 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 425 426 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 427 { 428 printf("resetting ...\n"); 429 430 /* wait 50 ms */ 431 udelay(50000); 432 disable_interrupts(); 433 reset_cpu(0); 434 435 /*NOTREACHED*/ 436 return 0; 437 } 438 439 void flush_cache(unsigned long dummy1, unsigned long dummy2) 440 { 441 asm("wbinvd\n"); 442 } 443 444 __weak void reset_cpu(ulong addr) 445 { 446 /* Do a hard reset through the chipset's reset control register */ 447 outb(SYS_RST | RST_CPU, PORT_RESET); 448 for (;;) 449 cpu_hlt(); 450 } 451 452 void x86_full_reset(void) 453 { 454 outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET); 455 } 456 457 int dcache_status(void) 458 { 459 return !(read_cr0() & 0x40000000); 460 } 461 462 /* Define these functions to allow ehch-hcd to function */ 463 void flush_dcache_range(unsigned long start, unsigned long stop) 464 { 465 } 466 467 void invalidate_dcache_range(unsigned long start, unsigned long stop) 468 { 469 } 470 471 void dcache_enable(void) 472 { 473 enable_caches(); 474 } 475 476 void dcache_disable(void) 477 { 478 disable_caches(); 479 } 480 481 void icache_enable(void) 482 { 483 } 484 485 void icache_disable(void) 486 { 487 } 488 489 int icache_status(void) 490 { 491 return 1; 492 } 493 494 void cpu_enable_paging_pae(ulong cr3) 495 { 496 __asm__ __volatile__( 497 /* Load the page table address */ 498 "movl %0, %%cr3\n" 499 /* Enable pae */ 500 "movl %%cr4, %%eax\n" 501 "orl $0x00000020, %%eax\n" 502 "movl %%eax, %%cr4\n" 503 /* Enable paging */ 504 "movl %%cr0, %%eax\n" 505 "orl $0x80000000, %%eax\n" 506 "movl %%eax, %%cr0\n" 507 : 508 : "r" (cr3) 509 : "eax"); 510 } 511 512 void cpu_disable_paging_pae(void) 513 { 514 /* Turn off paging */ 515 __asm__ __volatile__ ( 516 /* Disable paging */ 517 "movl %%cr0, %%eax\n" 518 "andl $0x7fffffff, %%eax\n" 519 "movl %%eax, %%cr0\n" 520 /* Disable pae */ 521 "movl %%cr4, %%eax\n" 522 "andl $0xffffffdf, %%eax\n" 523 "movl %%eax, %%cr4\n" 524 : 525 : 526 : "eax"); 527 } 528 529 static bool can_detect_long_mode(void) 530 { 531 return cpuid_eax(0x80000000) > 0x80000000UL; 532 } 533 534 static bool has_long_mode(void) 535 { 536 return cpuid_edx(0x80000001) & (1 << 29) ? true : false; 537 } 538 539 int cpu_has_64bit(void) 540 { 541 return has_cpuid() && can_detect_long_mode() && 542 has_long_mode(); 543 } 544 545 const char *cpu_vendor_name(int vendor) 546 { 547 const char *name; 548 name = "<invalid cpu vendor>"; 549 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && 550 (x86_vendor_name[vendor] != 0)) 551 name = x86_vendor_name[vendor]; 552 553 return name; 554 } 555 556 char *cpu_get_name(char *name) 557 { 558 unsigned int *name_as_ints = (unsigned int *)name; 559 struct cpuid_result regs; 560 char *ptr; 561 int i; 562 563 /* This bit adds up to 48 bytes */ 564 for (i = 0; i < 3; i++) { 565 regs = cpuid(0x80000002 + i); 566 name_as_ints[i * 4 + 0] = regs.eax; 567 name_as_ints[i * 4 + 1] = regs.ebx; 568 name_as_ints[i * 4 + 2] = regs.ecx; 569 name_as_ints[i * 4 + 3] = regs.edx; 570 } 571 name[CPU_MAX_NAME_LEN - 1] = '\0'; 572 573 /* Skip leading spaces. */ 574 ptr = name; 575 while (*ptr == ' ') 576 ptr++; 577 578 return ptr; 579 } 580 581 int default_print_cpuinfo(void) 582 { 583 printf("CPU: %s, vendor %s, device %xh\n", 584 cpu_has_64bit() ? "x86_64" : "x86", 585 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); 586 587 return 0; 588 } 589 590 #define PAGETABLE_SIZE (6 * 4096) 591 592 /** 593 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode 594 * 595 * @pgtable: Pointer to a 24iKB block of memory 596 */ 597 static void build_pagetable(uint32_t *pgtable) 598 { 599 uint i; 600 601 memset(pgtable, '\0', PAGETABLE_SIZE); 602 603 /* Level 4 needs a single entry */ 604 pgtable[0] = (uint32_t)&pgtable[1024] + 7; 605 606 /* Level 3 has one 64-bit entry for each GiB of memory */ 607 for (i = 0; i < 4; i++) { 608 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + 609 0x1000 * i + 7; 610 } 611 612 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ 613 for (i = 0; i < 2048; i++) 614 pgtable[2048 + i * 2] = 0x183 + (i << 21UL); 615 } 616 617 int cpu_jump_to_64bit(ulong setup_base, ulong target) 618 { 619 uint32_t *pgtable; 620 621 pgtable = memalign(4096, PAGETABLE_SIZE); 622 if (!pgtable) 623 return -ENOMEM; 624 625 build_pagetable(pgtable); 626 cpu_call64((ulong)pgtable, setup_base, target); 627 free(pgtable); 628 629 return -EFAULT; 630 } 631 632 void show_boot_progress(int val) 633 { 634 #if MIN_PORT80_KCLOCKS_DELAY 635 /* 636 * Scale the time counter reading to avoid using 64 bit arithmetics. 637 * Can't use get_timer() here becuase it could be not yet 638 * initialized or even implemented. 639 */ 640 if (!gd->arch.tsc_prev) { 641 gd->arch.tsc_base_kclocks = rdtsc() / 1000; 642 gd->arch.tsc_prev = 0; 643 } else { 644 uint32_t now; 645 646 do { 647 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; 648 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); 649 gd->arch.tsc_prev = now; 650 } 651 #endif 652 outb(val, POST_PORT); 653 } 654 655 #ifndef CONFIG_SYS_COREBOOT 656 int last_stage_init(void) 657 { 658 write_tables(); 659 660 return 0; 661 } 662 #endif 663 664 #ifdef CONFIG_SMP 665 static int enable_smis(struct udevice *cpu, void *unused) 666 { 667 return 0; 668 } 669 670 static struct mp_flight_record mp_steps[] = { 671 MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL), 672 /* Wait for APs to finish initialization before proceeding */ 673 MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), 674 }; 675 676 static int x86_mp_init(void) 677 { 678 struct mp_params mp_params; 679 680 mp_params.parallel_microcode_load = 0, 681 mp_params.flight_plan = &mp_steps[0]; 682 mp_params.num_records = ARRAY_SIZE(mp_steps); 683 mp_params.microcode_pointer = 0; 684 685 if (mp_init(&mp_params)) { 686 printf("Warning: MP init failure\n"); 687 return -EIO; 688 } 689 690 return 0; 691 } 692 #endif 693 694 __weak int x86_init_cpus(void) 695 { 696 #ifdef CONFIG_SMP 697 debug("Init additional CPUs\n"); 698 x86_mp_init(); 699 #endif 700 701 return 0; 702 } 703 704 int cpu_init_r(void) 705 { 706 return x86_init_cpus(); 707 } 708