1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * SPDX-License-Identifier: GPL-2.0+ 17 */ 18 19 #include <common.h> 20 #include <command.h> 21 #include <asm/control_regs.h> 22 #include <asm/processor.h> 23 #include <asm/processor-flags.h> 24 #include <asm/interrupt.h> 25 #include <linux/compiler.h> 26 27 /* 28 * Constructor for a conventional segment GDT (or LDT) entry 29 * This is a macro so it can be used in initialisers 30 */ 31 #define GDT_ENTRY(flags, base, limit) \ 32 ((((base) & 0xff000000ULL) << (56-24)) | \ 33 (((flags) & 0x0000f0ffULL) << 40) | \ 34 (((limit) & 0x000f0000ULL) << (48-16)) | \ 35 (((base) & 0x00ffffffULL) << 16) | \ 36 (((limit) & 0x0000ffffULL))) 37 38 struct gdt_ptr { 39 u16 len; 40 u32 ptr; 41 } __packed; 42 43 static void load_ds(u32 segment) 44 { 45 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 46 } 47 48 static void load_es(u32 segment) 49 { 50 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 51 } 52 53 static void load_fs(u32 segment) 54 { 55 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 56 } 57 58 static void load_gs(u32 segment) 59 { 60 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 61 } 62 63 static void load_ss(u32 segment) 64 { 65 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 66 } 67 68 static void load_gdt(const u64 *boot_gdt, u16 num_entries) 69 { 70 struct gdt_ptr gdt; 71 72 gdt.len = (num_entries * 8) - 1; 73 gdt.ptr = (u32)boot_gdt; 74 75 asm volatile("lgdtl %0\n" : : "m" (gdt)); 76 } 77 78 void setup_gdt(gd_t *id, u64 *gdt_addr) 79 { 80 /* CS: code, read/execute, 4 GB, base 0 */ 81 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); 82 83 /* DS: data, read/write, 4 GB, base 0 */ 84 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); 85 86 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ 87 id->arch.gd_addr = id; 88 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, 89 (ulong)&id->arch.gd_addr, 0xfffff); 90 91 /* 16-bit CS: code, read/execute, 64 kB, base 0 */ 92 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff); 93 94 /* 16-bit DS: data, read/write, 64 kB, base 0 */ 95 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff); 96 97 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); 98 load_ds(X86_GDT_ENTRY_32BIT_DS); 99 load_es(X86_GDT_ENTRY_32BIT_DS); 100 load_gs(X86_GDT_ENTRY_32BIT_DS); 101 load_ss(X86_GDT_ENTRY_32BIT_DS); 102 load_fs(X86_GDT_ENTRY_32BIT_FS); 103 } 104 105 int __weak x86_cleanup_before_linux(void) 106 { 107 #ifdef CONFIG_BOOTSTAGE_STASH 108 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH, 109 CONFIG_BOOTSTAGE_STASH_SIZE); 110 #endif 111 112 return 0; 113 } 114 115 int x86_cpu_init_f(void) 116 { 117 const u32 em_rst = ~X86_CR0_EM; 118 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; 119 120 /* initialize FPU, reset EM, set MP and NE */ 121 asm ("fninit\n" \ 122 "movl %%cr0, %%eax\n" \ 123 "andl %0, %%eax\n" \ 124 "orl %1, %%eax\n" \ 125 "movl %%eax, %%cr0\n" \ 126 : : "i" (em_rst), "i" (mp_ne_set) : "eax"); 127 128 return 0; 129 } 130 int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f"))); 131 132 int x86_cpu_init_r(void) 133 { 134 /* Initialize core interrupt and exception functionality of CPU */ 135 cpu_init_interrupts(); 136 return 0; 137 } 138 int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); 139 140 void x86_enable_caches(void) 141 { 142 unsigned long cr0; 143 144 cr0 = read_cr0(); 145 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); 146 write_cr0(cr0); 147 wbinvd(); 148 } 149 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); 150 151 void x86_disable_caches(void) 152 { 153 unsigned long cr0; 154 155 cr0 = read_cr0(); 156 cr0 |= X86_CR0_NW | X86_CR0_CD; 157 wbinvd(); 158 write_cr0(cr0); 159 wbinvd(); 160 } 161 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); 162 163 int x86_init_cache(void) 164 { 165 enable_caches(); 166 167 return 0; 168 } 169 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 170 171 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 172 { 173 printf("resetting ...\n"); 174 175 /* wait 50 ms */ 176 udelay(50000); 177 disable_interrupts(); 178 reset_cpu(0); 179 180 /*NOTREACHED*/ 181 return 0; 182 } 183 184 void flush_cache(unsigned long dummy1, unsigned long dummy2) 185 { 186 asm("wbinvd\n"); 187 } 188 189 void __attribute__ ((regparm(0))) generate_gpf(void); 190 191 /* segment 0x70 is an arbitrary segment which does not exist */ 192 asm(".globl generate_gpf\n" 193 ".hidden generate_gpf\n" 194 ".type generate_gpf, @function\n" 195 "generate_gpf:\n" 196 "ljmp $0x70, $0x47114711\n"); 197 198 void __reset_cpu(ulong addr) 199 { 200 printf("Resetting using x86 Triple Fault\n"); 201 set_vector(13, generate_gpf); /* general protection fault handler */ 202 set_vector(8, generate_gpf); /* double fault handler */ 203 generate_gpf(); /* start the show */ 204 } 205 void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu"))); 206 207 int dcache_status(void) 208 { 209 return !(read_cr0() & 0x40000000); 210 } 211 212 /* Define these functions to allow ehch-hcd to function */ 213 void flush_dcache_range(unsigned long start, unsigned long stop) 214 { 215 } 216 217 void invalidate_dcache_range(unsigned long start, unsigned long stop) 218 { 219 } 220 221 void dcache_enable(void) 222 { 223 enable_caches(); 224 } 225 226 void dcache_disable(void) 227 { 228 disable_caches(); 229 } 230 231 void icache_enable(void) 232 { 233 } 234 235 void icache_disable(void) 236 { 237 } 238 239 int icache_status(void) 240 { 241 return 1; 242 } 243