1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * Part of this file is adapted from coreboot 17 * src/arch/x86/lib/cpu.c 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22 #include <common.h> 23 #include <command.h> 24 #include <dm.h> 25 #include <errno.h> 26 #include <malloc.h> 27 #include <asm/control_regs.h> 28 #include <asm/cpu.h> 29 #include <asm/lapic.h> 30 #include <asm/mp.h> 31 #include <asm/post.h> 32 #include <asm/processor.h> 33 #include <asm/processor-flags.h> 34 #include <asm/interrupt.h> 35 #include <asm/tables.h> 36 #include <linux/compiler.h> 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 /* 41 * Constructor for a conventional segment GDT (or LDT) entry 42 * This is a macro so it can be used in initialisers 43 */ 44 #define GDT_ENTRY(flags, base, limit) \ 45 ((((base) & 0xff000000ULL) << (56-24)) | \ 46 (((flags) & 0x0000f0ffULL) << 40) | \ 47 (((limit) & 0x000f0000ULL) << (48-16)) | \ 48 (((base) & 0x00ffffffULL) << 16) | \ 49 (((limit) & 0x0000ffffULL))) 50 51 struct gdt_ptr { 52 u16 len; 53 u32 ptr; 54 } __packed; 55 56 struct cpu_device_id { 57 unsigned vendor; 58 unsigned device; 59 }; 60 61 struct cpuinfo_x86 { 62 uint8_t x86; /* CPU family */ 63 uint8_t x86_vendor; /* CPU vendor */ 64 uint8_t x86_model; 65 uint8_t x86_mask; 66 }; 67 68 /* 69 * List of cpu vendor strings along with their normalized 70 * id values. 71 */ 72 static struct { 73 int vendor; 74 const char *name; 75 } x86_vendors[] = { 76 { X86_VENDOR_INTEL, "GenuineIntel", }, 77 { X86_VENDOR_CYRIX, "CyrixInstead", }, 78 { X86_VENDOR_AMD, "AuthenticAMD", }, 79 { X86_VENDOR_UMC, "UMC UMC UMC ", }, 80 { X86_VENDOR_NEXGEN, "NexGenDriven", }, 81 { X86_VENDOR_CENTAUR, "CentaurHauls", }, 82 { X86_VENDOR_RISE, "RiseRiseRise", }, 83 { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, 84 { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, 85 { X86_VENDOR_NSC, "Geode by NSC", }, 86 { X86_VENDOR_SIS, "SiS SiS SiS ", }, 87 }; 88 89 static const char *const x86_vendor_name[] = { 90 [X86_VENDOR_INTEL] = "Intel", 91 [X86_VENDOR_CYRIX] = "Cyrix", 92 [X86_VENDOR_AMD] = "AMD", 93 [X86_VENDOR_UMC] = "UMC", 94 [X86_VENDOR_NEXGEN] = "NexGen", 95 [X86_VENDOR_CENTAUR] = "Centaur", 96 [X86_VENDOR_RISE] = "Rise", 97 [X86_VENDOR_TRANSMETA] = "Transmeta", 98 [X86_VENDOR_NSC] = "NSC", 99 [X86_VENDOR_SIS] = "SiS", 100 }; 101 102 static void load_ds(u32 segment) 103 { 104 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 105 } 106 107 static void load_es(u32 segment) 108 { 109 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 110 } 111 112 static void load_fs(u32 segment) 113 { 114 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 115 } 116 117 static void load_gs(u32 segment) 118 { 119 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 120 } 121 122 static void load_ss(u32 segment) 123 { 124 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 125 } 126 127 static void load_gdt(const u64 *boot_gdt, u16 num_entries) 128 { 129 struct gdt_ptr gdt; 130 131 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; 132 gdt.ptr = (u32)boot_gdt; 133 134 asm volatile("lgdtl %0\n" : : "m" (gdt)); 135 } 136 137 void setup_gdt(gd_t *id, u64 *gdt_addr) 138 { 139 id->arch.gdt = gdt_addr; 140 /* CS: code, read/execute, 4 GB, base 0 */ 141 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); 142 143 /* DS: data, read/write, 4 GB, base 0 */ 144 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); 145 146 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ 147 id->arch.gd_addr = id; 148 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, 149 (ulong)&id->arch.gd_addr, 0xfffff); 150 151 /* 16-bit CS: code, read/execute, 64 kB, base 0 */ 152 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); 153 154 /* 16-bit DS: data, read/write, 64 kB, base 0 */ 155 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); 156 157 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); 158 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); 159 160 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); 161 load_ds(X86_GDT_ENTRY_32BIT_DS); 162 load_es(X86_GDT_ENTRY_32BIT_DS); 163 load_gs(X86_GDT_ENTRY_32BIT_DS); 164 load_ss(X86_GDT_ENTRY_32BIT_DS); 165 load_fs(X86_GDT_ENTRY_32BIT_FS); 166 } 167 168 #ifdef CONFIG_HAVE_FSP 169 /* 170 * Setup FSP execution environment GDT 171 * 172 * Per Intel FSP external architecture specification, before calling any FSP 173 * APIs, we need make sure the system is in flat 32-bit mode and both the code 174 * and data selectors should have full 4GB access range. Here we reuse the one 175 * we used in arch/x86/cpu/start16.S, and reload the segement registers. 176 */ 177 void setup_fsp_gdt(void) 178 { 179 load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4); 180 load_ds(X86_GDT_ENTRY_32BIT_DS); 181 load_ss(X86_GDT_ENTRY_32BIT_DS); 182 load_es(X86_GDT_ENTRY_32BIT_DS); 183 load_fs(X86_GDT_ENTRY_32BIT_DS); 184 load_gs(X86_GDT_ENTRY_32BIT_DS); 185 } 186 #endif 187 188 int __weak x86_cleanup_before_linux(void) 189 { 190 #ifdef CONFIG_BOOTSTAGE_STASH 191 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, 192 CONFIG_BOOTSTAGE_STASH_SIZE); 193 #endif 194 195 return 0; 196 } 197 198 /* 199 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected 200 * by the fact that they preserve the flags across the division of 5/2. 201 * PII and PPro exhibit this behavior too, but they have cpuid available. 202 */ 203 204 /* 205 * Perform the Cyrix 5/2 test. A Cyrix won't change 206 * the flags, while other 486 chips will. 207 */ 208 static inline int test_cyrix_52div(void) 209 { 210 unsigned int test; 211 212 __asm__ __volatile__( 213 "sahf\n\t" /* clear flags (%eax = 0x0005) */ 214 "div %b2\n\t" /* divide 5 by 2 */ 215 "lahf" /* store flags into %ah */ 216 : "=a" (test) 217 : "0" (5), "q" (2) 218 : "cc"); 219 220 /* AH is 0x02 on Cyrix after the divide.. */ 221 return (unsigned char) (test >> 8) == 0x02; 222 } 223 224 /* 225 * Detect a NexGen CPU running without BIOS hypercode new enough 226 * to have CPUID. (Thanks to Herbert Oppmann) 227 */ 228 229 static int deep_magic_nexgen_probe(void) 230 { 231 int ret; 232 233 __asm__ __volatile__ ( 234 " movw $0x5555, %%ax\n" 235 " xorw %%dx,%%dx\n" 236 " movw $2, %%cx\n" 237 " divw %%cx\n" 238 " movl $0, %%eax\n" 239 " jnz 1f\n" 240 " movl $1, %%eax\n" 241 "1:\n" 242 : "=a" (ret) : : "cx", "dx"); 243 return ret; 244 } 245 246 static bool has_cpuid(void) 247 { 248 return flag_is_changeable_p(X86_EFLAGS_ID); 249 } 250 251 static bool has_mtrr(void) 252 { 253 return cpuid_edx(0x00000001) & (1 << 12) ? true : false; 254 } 255 256 static int build_vendor_name(char *vendor_name) 257 { 258 struct cpuid_result result; 259 result = cpuid(0x00000000); 260 unsigned int *name_as_ints = (unsigned int *)vendor_name; 261 262 name_as_ints[0] = result.ebx; 263 name_as_ints[1] = result.edx; 264 name_as_ints[2] = result.ecx; 265 266 return result.eax; 267 } 268 269 static void identify_cpu(struct cpu_device_id *cpu) 270 { 271 char vendor_name[16]; 272 int i; 273 274 vendor_name[0] = '\0'; /* Unset */ 275 cpu->device = 0; /* fix gcc 4.4.4 warning */ 276 277 /* Find the id and vendor_name */ 278 if (!has_cpuid()) { 279 /* Its a 486 if we can modify the AC flag */ 280 if (flag_is_changeable_p(X86_EFLAGS_AC)) 281 cpu->device = 0x00000400; /* 486 */ 282 else 283 cpu->device = 0x00000300; /* 386 */ 284 if ((cpu->device == 0x00000400) && test_cyrix_52div()) { 285 memcpy(vendor_name, "CyrixInstead", 13); 286 /* If we ever care we can enable cpuid here */ 287 } 288 /* Detect NexGen with old hypercode */ 289 else if (deep_magic_nexgen_probe()) 290 memcpy(vendor_name, "NexGenDriven", 13); 291 } 292 if (has_cpuid()) { 293 int cpuid_level; 294 295 cpuid_level = build_vendor_name(vendor_name); 296 vendor_name[12] = '\0'; 297 298 /* Intel-defined flags: level 0x00000001 */ 299 if (cpuid_level >= 0x00000001) { 300 cpu->device = cpuid_eax(0x00000001); 301 } else { 302 /* Have CPUID level 0 only unheard of */ 303 cpu->device = 0x00000400; 304 } 305 } 306 cpu->vendor = X86_VENDOR_UNKNOWN; 307 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { 308 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { 309 cpu->vendor = x86_vendors[i].vendor; 310 break; 311 } 312 } 313 } 314 315 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) 316 { 317 c->x86 = (tfms >> 8) & 0xf; 318 c->x86_model = (tfms >> 4) & 0xf; 319 c->x86_mask = tfms & 0xf; 320 if (c->x86 == 0xf) 321 c->x86 += (tfms >> 20) & 0xff; 322 if (c->x86 >= 0x6) 323 c->x86_model += ((tfms >> 16) & 0xF) << 4; 324 } 325 326 int x86_cpu_init_f(void) 327 { 328 const u32 em_rst = ~X86_CR0_EM; 329 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; 330 331 /* initialize FPU, reset EM, set MP and NE */ 332 asm ("fninit\n" \ 333 "movl %%cr0, %%eax\n" \ 334 "andl %0, %%eax\n" \ 335 "orl %1, %%eax\n" \ 336 "movl %%eax, %%cr0\n" \ 337 : : "i" (em_rst), "i" (mp_ne_set) : "eax"); 338 339 /* identify CPU via cpuid and store the decoded info into gd->arch */ 340 if (has_cpuid()) { 341 struct cpu_device_id cpu; 342 struct cpuinfo_x86 c; 343 344 identify_cpu(&cpu); 345 get_fms(&c, cpu.device); 346 gd->arch.x86 = c.x86; 347 gd->arch.x86_vendor = cpu.vendor; 348 gd->arch.x86_model = c.x86_model; 349 gd->arch.x86_mask = c.x86_mask; 350 gd->arch.x86_device = cpu.device; 351 352 gd->arch.has_mtrr = has_mtrr(); 353 } 354 355 return 0; 356 } 357 358 void x86_enable_caches(void) 359 { 360 unsigned long cr0; 361 362 cr0 = read_cr0(); 363 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); 364 write_cr0(cr0); 365 wbinvd(); 366 } 367 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); 368 369 void x86_disable_caches(void) 370 { 371 unsigned long cr0; 372 373 cr0 = read_cr0(); 374 cr0 |= X86_CR0_NW | X86_CR0_CD; 375 wbinvd(); 376 write_cr0(cr0); 377 wbinvd(); 378 } 379 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); 380 381 int x86_init_cache(void) 382 { 383 enable_caches(); 384 385 return 0; 386 } 387 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 388 389 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 390 { 391 printf("resetting ...\n"); 392 393 /* wait 50 ms */ 394 udelay(50000); 395 disable_interrupts(); 396 reset_cpu(0); 397 398 /*NOTREACHED*/ 399 return 0; 400 } 401 402 void flush_cache(unsigned long dummy1, unsigned long dummy2) 403 { 404 asm("wbinvd\n"); 405 } 406 407 __weak void reset_cpu(ulong addr) 408 { 409 /* Do a hard reset through the chipset's reset control register */ 410 outb(SYS_RST | RST_CPU, PORT_RESET); 411 for (;;) 412 cpu_hlt(); 413 } 414 415 void x86_full_reset(void) 416 { 417 outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET); 418 } 419 420 int dcache_status(void) 421 { 422 return !(read_cr0() & 0x40000000); 423 } 424 425 /* Define these functions to allow ehch-hcd to function */ 426 void flush_dcache_range(unsigned long start, unsigned long stop) 427 { 428 } 429 430 void invalidate_dcache_range(unsigned long start, unsigned long stop) 431 { 432 } 433 434 void dcache_enable(void) 435 { 436 enable_caches(); 437 } 438 439 void dcache_disable(void) 440 { 441 disable_caches(); 442 } 443 444 void icache_enable(void) 445 { 446 } 447 448 void icache_disable(void) 449 { 450 } 451 452 int icache_status(void) 453 { 454 return 1; 455 } 456 457 void cpu_enable_paging_pae(ulong cr3) 458 { 459 __asm__ __volatile__( 460 /* Load the page table address */ 461 "movl %0, %%cr3\n" 462 /* Enable pae */ 463 "movl %%cr4, %%eax\n" 464 "orl $0x00000020, %%eax\n" 465 "movl %%eax, %%cr4\n" 466 /* Enable paging */ 467 "movl %%cr0, %%eax\n" 468 "orl $0x80000000, %%eax\n" 469 "movl %%eax, %%cr0\n" 470 : 471 : "r" (cr3) 472 : "eax"); 473 } 474 475 void cpu_disable_paging_pae(void) 476 { 477 /* Turn off paging */ 478 __asm__ __volatile__ ( 479 /* Disable paging */ 480 "movl %%cr0, %%eax\n" 481 "andl $0x7fffffff, %%eax\n" 482 "movl %%eax, %%cr0\n" 483 /* Disable pae */ 484 "movl %%cr4, %%eax\n" 485 "andl $0xffffffdf, %%eax\n" 486 "movl %%eax, %%cr4\n" 487 : 488 : 489 : "eax"); 490 } 491 492 static bool can_detect_long_mode(void) 493 { 494 return cpuid_eax(0x80000000) > 0x80000000UL; 495 } 496 497 static bool has_long_mode(void) 498 { 499 return cpuid_edx(0x80000001) & (1 << 29) ? true : false; 500 } 501 502 int cpu_has_64bit(void) 503 { 504 return has_cpuid() && can_detect_long_mode() && 505 has_long_mode(); 506 } 507 508 const char *cpu_vendor_name(int vendor) 509 { 510 const char *name; 511 name = "<invalid cpu vendor>"; 512 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && 513 (x86_vendor_name[vendor] != 0)) 514 name = x86_vendor_name[vendor]; 515 516 return name; 517 } 518 519 char *cpu_get_name(char *name) 520 { 521 unsigned int *name_as_ints = (unsigned int *)name; 522 struct cpuid_result regs; 523 char *ptr; 524 int i; 525 526 /* This bit adds up to 48 bytes */ 527 for (i = 0; i < 3; i++) { 528 regs = cpuid(0x80000002 + i); 529 name_as_ints[i * 4 + 0] = regs.eax; 530 name_as_ints[i * 4 + 1] = regs.ebx; 531 name_as_ints[i * 4 + 2] = regs.ecx; 532 name_as_ints[i * 4 + 3] = regs.edx; 533 } 534 name[CPU_MAX_NAME_LEN - 1] = '\0'; 535 536 /* Skip leading spaces. */ 537 ptr = name; 538 while (*ptr == ' ') 539 ptr++; 540 541 return ptr; 542 } 543 544 int default_print_cpuinfo(void) 545 { 546 printf("CPU: %s, vendor %s, device %xh\n", 547 cpu_has_64bit() ? "x86_64" : "x86", 548 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); 549 550 return 0; 551 } 552 553 #define PAGETABLE_SIZE (6 * 4096) 554 555 /** 556 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode 557 * 558 * @pgtable: Pointer to a 24iKB block of memory 559 */ 560 static void build_pagetable(uint32_t *pgtable) 561 { 562 uint i; 563 564 memset(pgtable, '\0', PAGETABLE_SIZE); 565 566 /* Level 4 needs a single entry */ 567 pgtable[0] = (uint32_t)&pgtable[1024] + 7; 568 569 /* Level 3 has one 64-bit entry for each GiB of memory */ 570 for (i = 0; i < 4; i++) { 571 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + 572 0x1000 * i + 7; 573 } 574 575 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ 576 for (i = 0; i < 2048; i++) 577 pgtable[2048 + i * 2] = 0x183 + (i << 21UL); 578 } 579 580 int cpu_jump_to_64bit(ulong setup_base, ulong target) 581 { 582 uint32_t *pgtable; 583 584 pgtable = memalign(4096, PAGETABLE_SIZE); 585 if (!pgtable) 586 return -ENOMEM; 587 588 build_pagetable(pgtable); 589 cpu_call64((ulong)pgtable, setup_base, target); 590 free(pgtable); 591 592 return -EFAULT; 593 } 594 595 void show_boot_progress(int val) 596 { 597 #if MIN_PORT80_KCLOCKS_DELAY 598 /* 599 * Scale the time counter reading to avoid using 64 bit arithmetics. 600 * Can't use get_timer() here becuase it could be not yet 601 * initialized or even implemented. 602 */ 603 if (!gd->arch.tsc_prev) { 604 gd->arch.tsc_base_kclocks = rdtsc() / 1000; 605 gd->arch.tsc_prev = 0; 606 } else { 607 uint32_t now; 608 609 do { 610 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; 611 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); 612 gd->arch.tsc_prev = now; 613 } 614 #endif 615 outb(val, POST_PORT); 616 } 617 618 #ifndef CONFIG_SYS_COREBOOT 619 int last_stage_init(void) 620 { 621 write_tables(); 622 623 return 0; 624 } 625 #endif 626 627 #ifdef CONFIG_SMP 628 static int enable_smis(struct udevice *cpu, void *unused) 629 { 630 return 0; 631 } 632 633 static struct mp_flight_record mp_steps[] = { 634 MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL), 635 /* Wait for APs to finish initialization before proceeding */ 636 MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), 637 }; 638 639 static int x86_mp_init(void) 640 { 641 struct mp_params mp_params; 642 643 mp_params.parallel_microcode_load = 0, 644 mp_params.flight_plan = &mp_steps[0]; 645 mp_params.num_records = ARRAY_SIZE(mp_steps); 646 mp_params.microcode_pointer = 0; 647 648 if (mp_init(&mp_params)) { 649 printf("Warning: MP init failure\n"); 650 return -EIO; 651 } 652 653 return 0; 654 } 655 #endif 656 657 __weak int x86_init_cpus(void) 658 { 659 #ifdef CONFIG_SMP 660 debug("Init additional CPUs\n"); 661 x86_mp_init(); 662 #endif 663 664 return 0; 665 } 666 667 int cpu_init_r(void) 668 { 669 return x86_init_cpus(); 670 } 671