xref: /openbmc/u-boot/arch/x86/cpu/cpu.c (revision 60570df1) 
1 /*
2  * (C) Copyright 2008-2011
3  * Graeme Russ, <graeme.russ@gmail.com>
4  *
5  * (C) Copyright 2002
6  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
7  *
8  * (C) Copyright 2002
9  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10  * Marius Groeger <mgroeger@sysgo.de>
11  *
12  * (C) Copyright 2002
13  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14  * Alex Zuepke <azu@sysgo.de>
15  *
16  * Part of this file is adapted from coreboot
17  * src/arch/x86/lib/cpu.c
18  *
19  * SPDX-License-Identifier:	GPL-2.0+
20  */
21 
22 #include <common.h>
23 #include <command.h>
24 #include <cpu.h>
25 #include <dm.h>
26 #include <errno.h>
27 #include <malloc.h>
28 #include <asm/control_regs.h>
29 #include <asm/cpu.h>
30 #include <asm/post.h>
31 #include <asm/processor.h>
32 #include <asm/processor-flags.h>
33 #include <asm/interrupt.h>
34 #include <asm/tables.h>
35 #include <linux/compiler.h>
36 
37 DECLARE_GLOBAL_DATA_PTR;
38 
39 /*
40  * Constructor for a conventional segment GDT (or LDT) entry
41  * This is a macro so it can be used in initialisers
42  */
43 #define GDT_ENTRY(flags, base, limit)			\
44 	((((base)  & 0xff000000ULL) << (56-24)) |	\
45 	 (((flags) & 0x0000f0ffULL) << 40) |		\
46 	 (((limit) & 0x000f0000ULL) << (48-16)) |	\
47 	 (((base)  & 0x00ffffffULL) << 16) |		\
48 	 (((limit) & 0x0000ffffULL)))
49 
50 struct gdt_ptr {
51 	u16 len;
52 	u32 ptr;
53 } __packed;
54 
55 struct cpu_device_id {
56 	unsigned vendor;
57 	unsigned device;
58 };
59 
60 struct cpuinfo_x86 {
61 	uint8_t x86;            /* CPU family */
62 	uint8_t x86_vendor;     /* CPU vendor */
63 	uint8_t x86_model;
64 	uint8_t x86_mask;
65 };
66 
67 /*
68  * List of cpu vendor strings along with their normalized
69  * id values.
70  */
71 static struct {
72 	int vendor;
73 	const char *name;
74 } x86_vendors[] = {
75 	{ X86_VENDOR_INTEL,     "GenuineIntel", },
76 	{ X86_VENDOR_CYRIX,     "CyrixInstead", },
77 	{ X86_VENDOR_AMD,       "AuthenticAMD", },
78 	{ X86_VENDOR_UMC,       "UMC UMC UMC ", },
79 	{ X86_VENDOR_NEXGEN,    "NexGenDriven", },
80 	{ X86_VENDOR_CENTAUR,   "CentaurHauls", },
81 	{ X86_VENDOR_RISE,      "RiseRiseRise", },
82 	{ X86_VENDOR_TRANSMETA, "GenuineTMx86", },
83 	{ X86_VENDOR_TRANSMETA, "TransmetaCPU", },
84 	{ X86_VENDOR_NSC,       "Geode by NSC", },
85 	{ X86_VENDOR_SIS,       "SiS SiS SiS ", },
86 };
87 
88 static const char *const x86_vendor_name[] = {
89 	[X86_VENDOR_INTEL]     = "Intel",
90 	[X86_VENDOR_CYRIX]     = "Cyrix",
91 	[X86_VENDOR_AMD]       = "AMD",
92 	[X86_VENDOR_UMC]       = "UMC",
93 	[X86_VENDOR_NEXGEN]    = "NexGen",
94 	[X86_VENDOR_CENTAUR]   = "Centaur",
95 	[X86_VENDOR_RISE]      = "Rise",
96 	[X86_VENDOR_TRANSMETA] = "Transmeta",
97 	[X86_VENDOR_NSC]       = "NSC",
98 	[X86_VENDOR_SIS]       = "SiS",
99 };
100 
101 static void load_ds(u32 segment)
102 {
103 	asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
104 }
105 
106 static void load_es(u32 segment)
107 {
108 	asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
109 }
110 
111 static void load_fs(u32 segment)
112 {
113 	asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
114 }
115 
116 static void load_gs(u32 segment)
117 {
118 	asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
119 }
120 
121 static void load_ss(u32 segment)
122 {
123 	asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
124 }
125 
126 static void load_gdt(const u64 *boot_gdt, u16 num_entries)
127 {
128 	struct gdt_ptr gdt;
129 
130 	gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
131 	gdt.ptr = (u32)boot_gdt;
132 
133 	asm volatile("lgdtl %0\n" : : "m" (gdt));
134 }
135 
136 void setup_gdt(gd_t *id, u64 *gdt_addr)
137 {
138 	id->arch.gdt = gdt_addr;
139 	/* CS: code, read/execute, 4 GB, base 0 */
140 	gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
141 
142 	/* DS: data, read/write, 4 GB, base 0 */
143 	gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
144 
145 	/* FS: data, read/write, 4 GB, base (Global Data Pointer) */
146 	id->arch.gd_addr = id;
147 	gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
148 		     (ulong)&id->arch.gd_addr, 0xfffff);
149 
150 	/* 16-bit CS: code, read/execute, 64 kB, base 0 */
151 	gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
152 
153 	/* 16-bit DS: data, read/write, 64 kB, base 0 */
154 	gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
155 
156 	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
157 	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
158 
159 	load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
160 	load_ds(X86_GDT_ENTRY_32BIT_DS);
161 	load_es(X86_GDT_ENTRY_32BIT_DS);
162 	load_gs(X86_GDT_ENTRY_32BIT_DS);
163 	load_ss(X86_GDT_ENTRY_32BIT_DS);
164 	load_fs(X86_GDT_ENTRY_32BIT_FS);
165 }
166 
167 int __weak x86_cleanup_before_linux(void)
168 {
169 #ifdef CONFIG_BOOTSTAGE_STASH
170 	bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
171 			CONFIG_BOOTSTAGE_STASH_SIZE);
172 #endif
173 
174 	return 0;
175 }
176 
177 /*
178  * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
179  * by the fact that they preserve the flags across the division of 5/2.
180  * PII and PPro exhibit this behavior too, but they have cpuid available.
181  */
182 
183 /*
184  * Perform the Cyrix 5/2 test. A Cyrix won't change
185  * the flags, while other 486 chips will.
186  */
187 static inline int test_cyrix_52div(void)
188 {
189 	unsigned int test;
190 
191 	__asm__ __volatile__(
192 	     "sahf\n\t"		/* clear flags (%eax = 0x0005) */
193 	     "div %b2\n\t"	/* divide 5 by 2 */
194 	     "lahf"		/* store flags into %ah */
195 	     : "=a" (test)
196 	     : "0" (5), "q" (2)
197 	     : "cc");
198 
199 	/* AH is 0x02 on Cyrix after the divide.. */
200 	return (unsigned char) (test >> 8) == 0x02;
201 }
202 
203 /*
204  *	Detect a NexGen CPU running without BIOS hypercode new enough
205  *	to have CPUID. (Thanks to Herbert Oppmann)
206  */
207 
208 static int deep_magic_nexgen_probe(void)
209 {
210 	int ret;
211 
212 	__asm__ __volatile__ (
213 		"	movw	$0x5555, %%ax\n"
214 		"	xorw	%%dx,%%dx\n"
215 		"	movw	$2, %%cx\n"
216 		"	divw	%%cx\n"
217 		"	movl	$0, %%eax\n"
218 		"	jnz	1f\n"
219 		"	movl	$1, %%eax\n"
220 		"1:\n"
221 		: "=a" (ret) : : "cx", "dx");
222 	return  ret;
223 }
224 
225 static bool has_cpuid(void)
226 {
227 	return flag_is_changeable_p(X86_EFLAGS_ID);
228 }
229 
230 static bool has_mtrr(void)
231 {
232 	return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
233 }
234 
235 static int build_vendor_name(char *vendor_name)
236 {
237 	struct cpuid_result result;
238 	result = cpuid(0x00000000);
239 	unsigned int *name_as_ints = (unsigned int *)vendor_name;
240 
241 	name_as_ints[0] = result.ebx;
242 	name_as_ints[1] = result.edx;
243 	name_as_ints[2] = result.ecx;
244 
245 	return result.eax;
246 }
247 
248 static void identify_cpu(struct cpu_device_id *cpu)
249 {
250 	char vendor_name[16];
251 	int i;
252 
253 	vendor_name[0] = '\0'; /* Unset */
254 	cpu->device = 0; /* fix gcc 4.4.4 warning */
255 
256 	/* Find the id and vendor_name */
257 	if (!has_cpuid()) {
258 		/* Its a 486 if we can modify the AC flag */
259 		if (flag_is_changeable_p(X86_EFLAGS_AC))
260 			cpu->device = 0x00000400; /* 486 */
261 		else
262 			cpu->device = 0x00000300; /* 386 */
263 		if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
264 			memcpy(vendor_name, "CyrixInstead", 13);
265 			/* If we ever care we can enable cpuid here */
266 		}
267 		/* Detect NexGen with old hypercode */
268 		else if (deep_magic_nexgen_probe())
269 			memcpy(vendor_name, "NexGenDriven", 13);
270 	}
271 	if (has_cpuid()) {
272 		int  cpuid_level;
273 
274 		cpuid_level = build_vendor_name(vendor_name);
275 		vendor_name[12] = '\0';
276 
277 		/* Intel-defined flags: level 0x00000001 */
278 		if (cpuid_level >= 0x00000001) {
279 			cpu->device = cpuid_eax(0x00000001);
280 		} else {
281 			/* Have CPUID level 0 only unheard of */
282 			cpu->device = 0x00000400;
283 		}
284 	}
285 	cpu->vendor = X86_VENDOR_UNKNOWN;
286 	for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
287 		if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
288 			cpu->vendor = x86_vendors[i].vendor;
289 			break;
290 		}
291 	}
292 }
293 
294 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
295 {
296 	c->x86 = (tfms >> 8) & 0xf;
297 	c->x86_model = (tfms >> 4) & 0xf;
298 	c->x86_mask = tfms & 0xf;
299 	if (c->x86 == 0xf)
300 		c->x86 += (tfms >> 20) & 0xff;
301 	if (c->x86 >= 0x6)
302 		c->x86_model += ((tfms >> 16) & 0xF) << 4;
303 }
304 
305 int x86_cpu_init_f(void)
306 {
307 	const u32 em_rst = ~X86_CR0_EM;
308 	const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
309 
310 	/* initialize FPU, reset EM, set MP and NE */
311 	asm ("fninit\n" \
312 	     "movl %%cr0, %%eax\n" \
313 	     "andl %0, %%eax\n" \
314 	     "orl  %1, %%eax\n" \
315 	     "movl %%eax, %%cr0\n" \
316 	     : : "i" (em_rst), "i" (mp_ne_set) : "eax");
317 
318 	/* identify CPU via cpuid and store the decoded info into gd->arch */
319 	if (has_cpuid()) {
320 		struct cpu_device_id cpu;
321 		struct cpuinfo_x86 c;
322 
323 		identify_cpu(&cpu);
324 		get_fms(&c, cpu.device);
325 		gd->arch.x86 = c.x86;
326 		gd->arch.x86_vendor = cpu.vendor;
327 		gd->arch.x86_model = c.x86_model;
328 		gd->arch.x86_mask = c.x86_mask;
329 		gd->arch.x86_device = cpu.device;
330 
331 		gd->arch.has_mtrr = has_mtrr();
332 	}
333 
334 	return 0;
335 }
336 
337 void x86_enable_caches(void)
338 {
339 	unsigned long cr0;
340 
341 	cr0 = read_cr0();
342 	cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
343 	write_cr0(cr0);
344 	wbinvd();
345 }
346 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
347 
348 void x86_disable_caches(void)
349 {
350 	unsigned long cr0;
351 
352 	cr0 = read_cr0();
353 	cr0 |= X86_CR0_NW | X86_CR0_CD;
354 	wbinvd();
355 	write_cr0(cr0);
356 	wbinvd();
357 }
358 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
359 
360 int x86_init_cache(void)
361 {
362 	enable_caches();
363 
364 	return 0;
365 }
366 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
367 
368 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
369 {
370 	printf("resetting ...\n");
371 
372 	/* wait 50 ms */
373 	udelay(50000);
374 	disable_interrupts();
375 	reset_cpu(0);
376 
377 	/*NOTREACHED*/
378 	return 0;
379 }
380 
381 void  flush_cache(unsigned long dummy1, unsigned long dummy2)
382 {
383 	asm("wbinvd\n");
384 }
385 
386 __weak void reset_cpu(ulong addr)
387 {
388 	/* Do a hard reset through the chipset's reset control register */
389 	outb(SYS_RST | RST_CPU, PORT_RESET);
390 	for (;;)
391 		cpu_hlt();
392 }
393 
394 void x86_full_reset(void)
395 {
396 	outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET);
397 }
398 
399 int dcache_status(void)
400 {
401 	return !(read_cr0() & 0x40000000);
402 }
403 
404 /* Define these functions to allow ehch-hcd to function */
405 void flush_dcache_range(unsigned long start, unsigned long stop)
406 {
407 }
408 
409 void invalidate_dcache_range(unsigned long start, unsigned long stop)
410 {
411 }
412 
413 void dcache_enable(void)
414 {
415 	enable_caches();
416 }
417 
418 void dcache_disable(void)
419 {
420 	disable_caches();
421 }
422 
423 void icache_enable(void)
424 {
425 }
426 
427 void icache_disable(void)
428 {
429 }
430 
431 int icache_status(void)
432 {
433 	return 1;
434 }
435 
436 void cpu_enable_paging_pae(ulong cr3)
437 {
438 	__asm__ __volatile__(
439 		/* Load the page table address */
440 		"movl	%0, %%cr3\n"
441 		/* Enable pae */
442 		"movl	%%cr4, %%eax\n"
443 		"orl	$0x00000020, %%eax\n"
444 		"movl	%%eax, %%cr4\n"
445 		/* Enable paging */
446 		"movl	%%cr0, %%eax\n"
447 		"orl	$0x80000000, %%eax\n"
448 		"movl	%%eax, %%cr0\n"
449 		:
450 		: "r" (cr3)
451 		: "eax");
452 }
453 
454 void cpu_disable_paging_pae(void)
455 {
456 	/* Turn off paging */
457 	__asm__ __volatile__ (
458 		/* Disable paging */
459 		"movl	%%cr0, %%eax\n"
460 		"andl	$0x7fffffff, %%eax\n"
461 		"movl	%%eax, %%cr0\n"
462 		/* Disable pae */
463 		"movl	%%cr4, %%eax\n"
464 		"andl	$0xffffffdf, %%eax\n"
465 		"movl	%%eax, %%cr4\n"
466 		:
467 		:
468 		: "eax");
469 }
470 
471 static bool can_detect_long_mode(void)
472 {
473 	return cpuid_eax(0x80000000) > 0x80000000UL;
474 }
475 
476 static bool has_long_mode(void)
477 {
478 	return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
479 }
480 
481 int cpu_has_64bit(void)
482 {
483 	return has_cpuid() && can_detect_long_mode() &&
484 		has_long_mode();
485 }
486 
487 const char *cpu_vendor_name(int vendor)
488 {
489 	const char *name;
490 	name = "<invalid cpu vendor>";
491 	if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
492 	    (x86_vendor_name[vendor] != 0))
493 		name = x86_vendor_name[vendor];
494 
495 	return name;
496 }
497 
498 char *cpu_get_name(char *name)
499 {
500 	unsigned int *name_as_ints = (unsigned int *)name;
501 	struct cpuid_result regs;
502 	char *ptr;
503 	int i;
504 
505 	/* This bit adds up to 48 bytes */
506 	for (i = 0; i < 3; i++) {
507 		regs = cpuid(0x80000002 + i);
508 		name_as_ints[i * 4 + 0] = regs.eax;
509 		name_as_ints[i * 4 + 1] = regs.ebx;
510 		name_as_ints[i * 4 + 2] = regs.ecx;
511 		name_as_ints[i * 4 + 3] = regs.edx;
512 	}
513 	name[CPU_MAX_NAME_LEN - 1] = '\0';
514 
515 	/* Skip leading spaces. */
516 	ptr = name;
517 	while (*ptr == ' ')
518 		ptr++;
519 
520 	return ptr;
521 }
522 
523 int x86_cpu_get_desc(struct udevice *dev, char *buf, int size)
524 {
525 	if (size < CPU_MAX_NAME_LEN)
526 		return -ENOSPC;
527 
528 	cpu_get_name(buf);
529 
530 	return 0;
531 }
532 
533 int default_print_cpuinfo(void)
534 {
535 	printf("CPU: %s, vendor %s, device %xh\n",
536 	       cpu_has_64bit() ? "x86_64" : "x86",
537 	       cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
538 
539 	return 0;
540 }
541 
542 #define PAGETABLE_SIZE		(6 * 4096)
543 
544 /**
545  * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
546  *
547  * @pgtable: Pointer to a 24iKB block of memory
548  */
549 static void build_pagetable(uint32_t *pgtable)
550 {
551 	uint i;
552 
553 	memset(pgtable, '\0', PAGETABLE_SIZE);
554 
555 	/* Level 4 needs a single entry */
556 	pgtable[0] = (uint32_t)&pgtable[1024] + 7;
557 
558 	/* Level 3 has one 64-bit entry for each GiB of memory */
559 	for (i = 0; i < 4; i++) {
560 		pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
561 							0x1000 * i + 7;
562 	}
563 
564 	/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
565 	for (i = 0; i < 2048; i++)
566 		pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
567 }
568 
569 int cpu_jump_to_64bit(ulong setup_base, ulong target)
570 {
571 	uint32_t *pgtable;
572 
573 	pgtable = memalign(4096, PAGETABLE_SIZE);
574 	if (!pgtable)
575 		return -ENOMEM;
576 
577 	build_pagetable(pgtable);
578 	cpu_call64((ulong)pgtable, setup_base, target);
579 	free(pgtable);
580 
581 	return -EFAULT;
582 }
583 
584 void show_boot_progress(int val)
585 {
586 #if MIN_PORT80_KCLOCKS_DELAY
587 	/*
588 	 * Scale the time counter reading to avoid using 64 bit arithmetics.
589 	 * Can't use get_timer() here becuase it could be not yet
590 	 * initialized or even implemented.
591 	 */
592 	if (!gd->arch.tsc_prev) {
593 		gd->arch.tsc_base_kclocks = rdtsc() / 1000;
594 		gd->arch.tsc_prev = 0;
595 	} else {
596 		uint32_t now;
597 
598 		do {
599 			now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
600 		} while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
601 		gd->arch.tsc_prev = now;
602 	}
603 #endif
604 	outb(val, POST_PORT);
605 }
606 
607 #ifndef CONFIG_SYS_COREBOOT
608 int last_stage_init(void)
609 {
610 	write_tables();
611 
612 	return 0;
613 }
614 #endif
615 
616 __weak int x86_init_cpus(void)
617 {
618 	return 0;
619 }
620 
621 int cpu_init_r(void)
622 {
623 	return x86_init_cpus();
624 }
625 
626 static const struct cpu_ops cpu_x86_ops = {
627 	.get_desc	= x86_cpu_get_desc,
628 };
629 
630 static const struct udevice_id cpu_x86_ids[] = {
631 	{ .compatible = "cpu-x86" },
632 	{ }
633 };
634 
635 U_BOOT_DRIVER(cpu_x86_drv) = {
636 	.name		= "cpu_x86",
637 	.id		= UCLASS_CPU,
638 	.of_match	= cpu_x86_ids,
639 	.ops		= &cpu_x86_ops,
640 };
641