1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * Part of this file is adapted from coreboot 17 * src/arch/x86/lib/cpu.c 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22 #include <common.h> 23 #include <command.h> 24 #include <dm.h> 25 #include <errno.h> 26 #include <malloc.h> 27 #include <asm/control_regs.h> 28 #include <asm/coreboot_tables.h> 29 #include <asm/cpu.h> 30 #include <asm/lapic.h> 31 #include <asm/microcode.h> 32 #include <asm/mp.h> 33 #include <asm/mrccache.h> 34 #include <asm/msr.h> 35 #include <asm/mtrr.h> 36 #include <asm/post.h> 37 #include <asm/processor.h> 38 #include <asm/processor-flags.h> 39 #include <asm/interrupt.h> 40 #include <asm/tables.h> 41 #include <linux/compiler.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 /* 46 * Constructor for a conventional segment GDT (or LDT) entry 47 * This is a macro so it can be used in initialisers 48 */ 49 #define GDT_ENTRY(flags, base, limit) \ 50 ((((base) & 0xff000000ULL) << (56-24)) | \ 51 (((flags) & 0x0000f0ffULL) << 40) | \ 52 (((limit) & 0x000f0000ULL) << (48-16)) | \ 53 (((base) & 0x00ffffffULL) << 16) | \ 54 (((limit) & 0x0000ffffULL))) 55 56 struct gdt_ptr { 57 u16 len; 58 u32 ptr; 59 } __packed; 60 61 struct cpu_device_id { 62 unsigned vendor; 63 unsigned device; 64 }; 65 66 struct cpuinfo_x86 { 67 uint8_t x86; /* CPU family */ 68 uint8_t x86_vendor; /* CPU vendor */ 69 uint8_t x86_model; 70 uint8_t x86_mask; 71 }; 72 73 /* 74 * List of cpu vendor strings along with their normalized 75 * id values. 76 */ 77 static const struct { 78 int vendor; 79 const char *name; 80 } x86_vendors[] = { 81 { X86_VENDOR_INTEL, "GenuineIntel", }, 82 { X86_VENDOR_CYRIX, "CyrixInstead", }, 83 { X86_VENDOR_AMD, "AuthenticAMD", }, 84 { X86_VENDOR_UMC, "UMC UMC UMC ", }, 85 { X86_VENDOR_NEXGEN, "NexGenDriven", }, 86 { X86_VENDOR_CENTAUR, "CentaurHauls", }, 87 { X86_VENDOR_RISE, "RiseRiseRise", }, 88 { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, 89 { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, 90 { X86_VENDOR_NSC, "Geode by NSC", }, 91 { X86_VENDOR_SIS, "SiS SiS SiS ", }, 92 }; 93 94 static const char *const x86_vendor_name[] = { 95 [X86_VENDOR_INTEL] = "Intel", 96 [X86_VENDOR_CYRIX] = "Cyrix", 97 [X86_VENDOR_AMD] = "AMD", 98 [X86_VENDOR_UMC] = "UMC", 99 [X86_VENDOR_NEXGEN] = "NexGen", 100 [X86_VENDOR_CENTAUR] = "Centaur", 101 [X86_VENDOR_RISE] = "Rise", 102 [X86_VENDOR_TRANSMETA] = "Transmeta", 103 [X86_VENDOR_NSC] = "NSC", 104 [X86_VENDOR_SIS] = "SiS", 105 }; 106 107 static void load_ds(u32 segment) 108 { 109 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 110 } 111 112 static void load_es(u32 segment) 113 { 114 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 115 } 116 117 static void load_fs(u32 segment) 118 { 119 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 120 } 121 122 static void load_gs(u32 segment) 123 { 124 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 125 } 126 127 static void load_ss(u32 segment) 128 { 129 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 130 } 131 132 static void load_gdt(const u64 *boot_gdt, u16 num_entries) 133 { 134 struct gdt_ptr gdt; 135 136 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; 137 gdt.ptr = (u32)boot_gdt; 138 139 asm volatile("lgdtl %0\n" : : "m" (gdt)); 140 } 141 142 void arch_setup_gd(gd_t *new_gd) 143 { 144 u64 *gdt_addr; 145 146 gdt_addr = new_gd->arch.gdt; 147 148 /* 149 * CS: code, read/execute, 4 GB, base 0 150 * 151 * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS 152 */ 153 gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff); 154 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); 155 156 /* DS: data, read/write, 4 GB, base 0 */ 157 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); 158 159 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ 160 new_gd->arch.gd_addr = new_gd; 161 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, 162 (ulong)&new_gd->arch.gd_addr, 0xfffff); 163 164 /* 16-bit CS: code, read/execute, 64 kB, base 0 */ 165 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); 166 167 /* 16-bit DS: data, read/write, 64 kB, base 0 */ 168 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); 169 170 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); 171 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); 172 173 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); 174 load_ds(X86_GDT_ENTRY_32BIT_DS); 175 load_es(X86_GDT_ENTRY_32BIT_DS); 176 load_gs(X86_GDT_ENTRY_32BIT_DS); 177 load_ss(X86_GDT_ENTRY_32BIT_DS); 178 load_fs(X86_GDT_ENTRY_32BIT_FS); 179 } 180 181 #ifdef CONFIG_HAVE_FSP 182 /* 183 * Setup FSP execution environment GDT 184 * 185 * Per Intel FSP external architecture specification, before calling any FSP 186 * APIs, we need make sure the system is in flat 32-bit mode and both the code 187 * and data selectors should have full 4GB access range. Here we reuse the one 188 * we used in arch/x86/cpu/start16.S, and reload the segement registers. 189 */ 190 void setup_fsp_gdt(void) 191 { 192 load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4); 193 load_ds(X86_GDT_ENTRY_32BIT_DS); 194 load_ss(X86_GDT_ENTRY_32BIT_DS); 195 load_es(X86_GDT_ENTRY_32BIT_DS); 196 load_fs(X86_GDT_ENTRY_32BIT_DS); 197 load_gs(X86_GDT_ENTRY_32BIT_DS); 198 } 199 #endif 200 201 int __weak x86_cleanup_before_linux(void) 202 { 203 #ifdef CONFIG_BOOTSTAGE_STASH 204 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, 205 CONFIG_BOOTSTAGE_STASH_SIZE); 206 #endif 207 208 return 0; 209 } 210 211 /* 212 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected 213 * by the fact that they preserve the flags across the division of 5/2. 214 * PII and PPro exhibit this behavior too, but they have cpuid available. 215 */ 216 217 /* 218 * Perform the Cyrix 5/2 test. A Cyrix won't change 219 * the flags, while other 486 chips will. 220 */ 221 static inline int test_cyrix_52div(void) 222 { 223 unsigned int test; 224 225 __asm__ __volatile__( 226 "sahf\n\t" /* clear flags (%eax = 0x0005) */ 227 "div %b2\n\t" /* divide 5 by 2 */ 228 "lahf" /* store flags into %ah */ 229 : "=a" (test) 230 : "0" (5), "q" (2) 231 : "cc"); 232 233 /* AH is 0x02 on Cyrix after the divide.. */ 234 return (unsigned char) (test >> 8) == 0x02; 235 } 236 237 /* 238 * Detect a NexGen CPU running without BIOS hypercode new enough 239 * to have CPUID. (Thanks to Herbert Oppmann) 240 */ 241 242 static int deep_magic_nexgen_probe(void) 243 { 244 int ret; 245 246 __asm__ __volatile__ ( 247 " movw $0x5555, %%ax\n" 248 " xorw %%dx,%%dx\n" 249 " movw $2, %%cx\n" 250 " divw %%cx\n" 251 " movl $0, %%eax\n" 252 " jnz 1f\n" 253 " movl $1, %%eax\n" 254 "1:\n" 255 : "=a" (ret) : : "cx", "dx"); 256 return ret; 257 } 258 259 static bool has_cpuid(void) 260 { 261 return flag_is_changeable_p(X86_EFLAGS_ID); 262 } 263 264 static bool has_mtrr(void) 265 { 266 return cpuid_edx(0x00000001) & (1 << 12) ? true : false; 267 } 268 269 static int build_vendor_name(char *vendor_name) 270 { 271 struct cpuid_result result; 272 result = cpuid(0x00000000); 273 unsigned int *name_as_ints = (unsigned int *)vendor_name; 274 275 name_as_ints[0] = result.ebx; 276 name_as_ints[1] = result.edx; 277 name_as_ints[2] = result.ecx; 278 279 return result.eax; 280 } 281 282 static void identify_cpu(struct cpu_device_id *cpu) 283 { 284 char vendor_name[16]; 285 int i; 286 287 vendor_name[0] = '\0'; /* Unset */ 288 cpu->device = 0; /* fix gcc 4.4.4 warning */ 289 290 /* Find the id and vendor_name */ 291 if (!has_cpuid()) { 292 /* Its a 486 if we can modify the AC flag */ 293 if (flag_is_changeable_p(X86_EFLAGS_AC)) 294 cpu->device = 0x00000400; /* 486 */ 295 else 296 cpu->device = 0x00000300; /* 386 */ 297 if ((cpu->device == 0x00000400) && test_cyrix_52div()) { 298 memcpy(vendor_name, "CyrixInstead", 13); 299 /* If we ever care we can enable cpuid here */ 300 } 301 /* Detect NexGen with old hypercode */ 302 else if (deep_magic_nexgen_probe()) 303 memcpy(vendor_name, "NexGenDriven", 13); 304 } 305 if (has_cpuid()) { 306 int cpuid_level; 307 308 cpuid_level = build_vendor_name(vendor_name); 309 vendor_name[12] = '\0'; 310 311 /* Intel-defined flags: level 0x00000001 */ 312 if (cpuid_level >= 0x00000001) { 313 cpu->device = cpuid_eax(0x00000001); 314 } else { 315 /* Have CPUID level 0 only unheard of */ 316 cpu->device = 0x00000400; 317 } 318 } 319 cpu->vendor = X86_VENDOR_UNKNOWN; 320 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { 321 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { 322 cpu->vendor = x86_vendors[i].vendor; 323 break; 324 } 325 } 326 } 327 328 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) 329 { 330 c->x86 = (tfms >> 8) & 0xf; 331 c->x86_model = (tfms >> 4) & 0xf; 332 c->x86_mask = tfms & 0xf; 333 if (c->x86 == 0xf) 334 c->x86 += (tfms >> 20) & 0xff; 335 if (c->x86 >= 0x6) 336 c->x86_model += ((tfms >> 16) & 0xF) << 4; 337 } 338 339 u32 cpu_get_family_model(void) 340 { 341 return gd->arch.x86_device & 0x0fff0ff0; 342 } 343 344 u32 cpu_get_stepping(void) 345 { 346 return gd->arch.x86_mask; 347 } 348 349 int x86_cpu_init_f(void) 350 { 351 const u32 em_rst = ~X86_CR0_EM; 352 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; 353 354 if (ll_boot_init()) { 355 /* initialize FPU, reset EM, set MP and NE */ 356 asm ("fninit\n" \ 357 "movl %%cr0, %%eax\n" \ 358 "andl %0, %%eax\n" \ 359 "orl %1, %%eax\n" \ 360 "movl %%eax, %%cr0\n" \ 361 : : "i" (em_rst), "i" (mp_ne_set) : "eax"); 362 } 363 364 /* identify CPU via cpuid and store the decoded info into gd->arch */ 365 if (has_cpuid()) { 366 struct cpu_device_id cpu; 367 struct cpuinfo_x86 c; 368 369 identify_cpu(&cpu); 370 get_fms(&c, cpu.device); 371 gd->arch.x86 = c.x86; 372 gd->arch.x86_vendor = cpu.vendor; 373 gd->arch.x86_model = c.x86_model; 374 gd->arch.x86_mask = c.x86_mask; 375 gd->arch.x86_device = cpu.device; 376 377 gd->arch.has_mtrr = has_mtrr(); 378 } 379 /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */ 380 gd->pci_ram_top = 0x80000000U; 381 382 /* Configure fixed range MTRRs for some legacy regions */ 383 if (gd->arch.has_mtrr) { 384 u64 mtrr_cap; 385 386 mtrr_cap = native_read_msr(MTRR_CAP_MSR); 387 if (mtrr_cap & MTRR_CAP_FIX) { 388 /* Mark the VGA RAM area as uncacheable */ 389 native_write_msr(MTRR_FIX_16K_A0000_MSR, 390 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE), 391 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); 392 393 /* 394 * Mark the PCI ROM area as cacheable to improve ROM 395 * execution performance. 396 */ 397 native_write_msr(MTRR_FIX_4K_C0000_MSR, 398 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 399 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 400 native_write_msr(MTRR_FIX_4K_C8000_MSR, 401 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 402 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 403 native_write_msr(MTRR_FIX_4K_D0000_MSR, 404 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 405 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 406 native_write_msr(MTRR_FIX_4K_D8000_MSR, 407 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 408 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 409 410 /* Enable the fixed range MTRRs */ 411 msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); 412 } 413 } 414 415 #ifdef CONFIG_I8254_TIMER 416 /* Set up the i8254 timer if required */ 417 i8254_init(); 418 #endif 419 420 return 0; 421 } 422 423 void x86_enable_caches(void) 424 { 425 unsigned long cr0; 426 427 cr0 = read_cr0(); 428 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); 429 write_cr0(cr0); 430 wbinvd(); 431 } 432 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); 433 434 void x86_disable_caches(void) 435 { 436 unsigned long cr0; 437 438 cr0 = read_cr0(); 439 cr0 |= X86_CR0_NW | X86_CR0_CD; 440 wbinvd(); 441 write_cr0(cr0); 442 wbinvd(); 443 } 444 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); 445 446 int x86_init_cache(void) 447 { 448 enable_caches(); 449 450 return 0; 451 } 452 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 453 454 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 455 { 456 printf("resetting ...\n"); 457 458 /* wait 50 ms */ 459 udelay(50000); 460 disable_interrupts(); 461 reset_cpu(0); 462 463 /*NOTREACHED*/ 464 return 0; 465 } 466 467 void flush_cache(unsigned long dummy1, unsigned long dummy2) 468 { 469 asm("wbinvd\n"); 470 } 471 472 __weak void reset_cpu(ulong addr) 473 { 474 /* Do a hard reset through the chipset's reset control register */ 475 outb(SYS_RST | RST_CPU, IO_PORT_RESET); 476 for (;;) 477 cpu_hlt(); 478 } 479 480 void x86_full_reset(void) 481 { 482 outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET); 483 } 484 485 int dcache_status(void) 486 { 487 return !(read_cr0() & X86_CR0_CD); 488 } 489 490 /* Define these functions to allow ehch-hcd to function */ 491 void flush_dcache_range(unsigned long start, unsigned long stop) 492 { 493 } 494 495 void invalidate_dcache_range(unsigned long start, unsigned long stop) 496 { 497 } 498 499 void dcache_enable(void) 500 { 501 enable_caches(); 502 } 503 504 void dcache_disable(void) 505 { 506 disable_caches(); 507 } 508 509 void icache_enable(void) 510 { 511 } 512 513 void icache_disable(void) 514 { 515 } 516 517 int icache_status(void) 518 { 519 return 1; 520 } 521 522 void cpu_enable_paging_pae(ulong cr3) 523 { 524 __asm__ __volatile__( 525 /* Load the page table address */ 526 "movl %0, %%cr3\n" 527 /* Enable pae */ 528 "movl %%cr4, %%eax\n" 529 "orl $0x00000020, %%eax\n" 530 "movl %%eax, %%cr4\n" 531 /* Enable paging */ 532 "movl %%cr0, %%eax\n" 533 "orl $0x80000000, %%eax\n" 534 "movl %%eax, %%cr0\n" 535 : 536 : "r" (cr3) 537 : "eax"); 538 } 539 540 void cpu_disable_paging_pae(void) 541 { 542 /* Turn off paging */ 543 __asm__ __volatile__ ( 544 /* Disable paging */ 545 "movl %%cr0, %%eax\n" 546 "andl $0x7fffffff, %%eax\n" 547 "movl %%eax, %%cr0\n" 548 /* Disable pae */ 549 "movl %%cr4, %%eax\n" 550 "andl $0xffffffdf, %%eax\n" 551 "movl %%eax, %%cr4\n" 552 : 553 : 554 : "eax"); 555 } 556 557 static bool can_detect_long_mode(void) 558 { 559 return cpuid_eax(0x80000000) > 0x80000000UL; 560 } 561 562 static bool has_long_mode(void) 563 { 564 return cpuid_edx(0x80000001) & (1 << 29) ? true : false; 565 } 566 567 int cpu_has_64bit(void) 568 { 569 return has_cpuid() && can_detect_long_mode() && 570 has_long_mode(); 571 } 572 573 const char *cpu_vendor_name(int vendor) 574 { 575 const char *name; 576 name = "<invalid cpu vendor>"; 577 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && 578 (x86_vendor_name[vendor] != 0)) 579 name = x86_vendor_name[vendor]; 580 581 return name; 582 } 583 584 char *cpu_get_name(char *name) 585 { 586 unsigned int *name_as_ints = (unsigned int *)name; 587 struct cpuid_result regs; 588 char *ptr; 589 int i; 590 591 /* This bit adds up to 48 bytes */ 592 for (i = 0; i < 3; i++) { 593 regs = cpuid(0x80000002 + i); 594 name_as_ints[i * 4 + 0] = regs.eax; 595 name_as_ints[i * 4 + 1] = regs.ebx; 596 name_as_ints[i * 4 + 2] = regs.ecx; 597 name_as_ints[i * 4 + 3] = regs.edx; 598 } 599 name[CPU_MAX_NAME_LEN - 1] = '\0'; 600 601 /* Skip leading spaces. */ 602 ptr = name; 603 while (*ptr == ' ') 604 ptr++; 605 606 return ptr; 607 } 608 609 int default_print_cpuinfo(void) 610 { 611 printf("CPU: %s, vendor %s, device %xh\n", 612 cpu_has_64bit() ? "x86_64" : "x86", 613 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); 614 615 return 0; 616 } 617 618 #define PAGETABLE_SIZE (6 * 4096) 619 620 /** 621 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode 622 * 623 * @pgtable: Pointer to a 24iKB block of memory 624 */ 625 static void build_pagetable(uint32_t *pgtable) 626 { 627 uint i; 628 629 memset(pgtable, '\0', PAGETABLE_SIZE); 630 631 /* Level 4 needs a single entry */ 632 pgtable[0] = (uint32_t)&pgtable[1024] + 7; 633 634 /* Level 3 has one 64-bit entry for each GiB of memory */ 635 for (i = 0; i < 4; i++) { 636 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + 637 0x1000 * i + 7; 638 } 639 640 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ 641 for (i = 0; i < 2048; i++) 642 pgtable[2048 + i * 2] = 0x183 + (i << 21UL); 643 } 644 645 int cpu_jump_to_64bit(ulong setup_base, ulong target) 646 { 647 uint32_t *pgtable; 648 649 pgtable = memalign(4096, PAGETABLE_SIZE); 650 if (!pgtable) 651 return -ENOMEM; 652 653 build_pagetable(pgtable); 654 cpu_call64((ulong)pgtable, setup_base, target); 655 free(pgtable); 656 657 return -EFAULT; 658 } 659 660 void show_boot_progress(int val) 661 { 662 outb(val, POST_PORT); 663 } 664 665 #ifndef CONFIG_SYS_COREBOOT 666 /* 667 * Implement a weak default function for boards that optionally 668 * need to clean up the system before jumping to the kernel. 669 */ 670 __weak void board_final_cleanup(void) 671 { 672 } 673 674 int last_stage_init(void) 675 { 676 write_tables(); 677 678 board_final_cleanup(); 679 680 return 0; 681 } 682 #endif 683 684 #ifdef CONFIG_SMP 685 static int enable_smis(struct udevice *cpu, void *unused) 686 { 687 return 0; 688 } 689 690 static struct mp_flight_record mp_steps[] = { 691 MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL), 692 /* Wait for APs to finish initialization before proceeding */ 693 MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), 694 }; 695 696 static int x86_mp_init(void) 697 { 698 struct mp_params mp_params; 699 700 mp_params.parallel_microcode_load = 0, 701 mp_params.flight_plan = &mp_steps[0]; 702 mp_params.num_records = ARRAY_SIZE(mp_steps); 703 mp_params.microcode_pointer = 0; 704 705 if (mp_init(&mp_params)) { 706 printf("Warning: MP init failure\n"); 707 return -EIO; 708 } 709 710 return 0; 711 } 712 #endif 713 714 static int x86_init_cpus(void) 715 { 716 #ifdef CONFIG_SMP 717 debug("Init additional CPUs\n"); 718 x86_mp_init(); 719 #else 720 struct udevice *dev; 721 722 /* 723 * This causes the cpu-x86 driver to be probed. 724 * We don't check return value here as we want to allow boards 725 * which have not been converted to use cpu uclass driver to boot. 726 */ 727 uclass_first_device(UCLASS_CPU, &dev); 728 #endif 729 730 return 0; 731 } 732 733 int cpu_init_r(void) 734 { 735 struct udevice *dev; 736 int ret; 737 738 if (!ll_boot_init()) 739 return 0; 740 741 ret = x86_init_cpus(); 742 if (ret) 743 return ret; 744 745 /* 746 * Set up the northbridge, PCH and LPC if available. Note that these 747 * may have had some limited pre-relocation init if they were probed 748 * before relocation, but this is post relocation. 749 */ 750 uclass_first_device(UCLASS_NORTHBRIDGE, &dev); 751 uclass_first_device(UCLASS_PCH, &dev); 752 uclass_first_device(UCLASS_LPC, &dev); 753 754 return 0; 755 } 756 757 #ifndef CONFIG_EFI_STUB 758 int reserve_arch(void) 759 { 760 #ifdef CONFIG_ENABLE_MRC_CACHE 761 mrccache_reserve(); 762 #endif 763 764 #ifdef CONFIG_SEABIOS 765 high_table_reserve(); 766 #endif 767 768 return 0; 769 } 770 #endif 771