1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * Part of this file is adapted from coreboot 17 * src/arch/x86/lib/cpu.c 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22 #include <common.h> 23 #include <command.h> 24 #include <dm.h> 25 #include <errno.h> 26 #include <malloc.h> 27 #include <asm/control_regs.h> 28 #include <asm/cpu.h> 29 #include <asm/lapic.h> 30 #include <asm/mp.h> 31 #include <asm/msr.h> 32 #include <asm/mtrr.h> 33 #include <asm/post.h> 34 #include <asm/processor.h> 35 #include <asm/processor-flags.h> 36 #include <asm/interrupt.h> 37 #include <asm/tables.h> 38 #include <linux/compiler.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 /* 43 * Constructor for a conventional segment GDT (or LDT) entry 44 * This is a macro so it can be used in initialisers 45 */ 46 #define GDT_ENTRY(flags, base, limit) \ 47 ((((base) & 0xff000000ULL) << (56-24)) | \ 48 (((flags) & 0x0000f0ffULL) << 40) | \ 49 (((limit) & 0x000f0000ULL) << (48-16)) | \ 50 (((base) & 0x00ffffffULL) << 16) | \ 51 (((limit) & 0x0000ffffULL))) 52 53 struct gdt_ptr { 54 u16 len; 55 u32 ptr; 56 } __packed; 57 58 struct cpu_device_id { 59 unsigned vendor; 60 unsigned device; 61 }; 62 63 struct cpuinfo_x86 { 64 uint8_t x86; /* CPU family */ 65 uint8_t x86_vendor; /* CPU vendor */ 66 uint8_t x86_model; 67 uint8_t x86_mask; 68 }; 69 70 /* 71 * List of cpu vendor strings along with their normalized 72 * id values. 73 */ 74 static struct { 75 int vendor; 76 const char *name; 77 } x86_vendors[] = { 78 { X86_VENDOR_INTEL, "GenuineIntel", }, 79 { X86_VENDOR_CYRIX, "CyrixInstead", }, 80 { X86_VENDOR_AMD, "AuthenticAMD", }, 81 { X86_VENDOR_UMC, "UMC UMC UMC ", }, 82 { X86_VENDOR_NEXGEN, "NexGenDriven", }, 83 { X86_VENDOR_CENTAUR, "CentaurHauls", }, 84 { X86_VENDOR_RISE, "RiseRiseRise", }, 85 { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, 86 { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, 87 { X86_VENDOR_NSC, "Geode by NSC", }, 88 { X86_VENDOR_SIS, "SiS SiS SiS ", }, 89 }; 90 91 static const char *const x86_vendor_name[] = { 92 [X86_VENDOR_INTEL] = "Intel", 93 [X86_VENDOR_CYRIX] = "Cyrix", 94 [X86_VENDOR_AMD] = "AMD", 95 [X86_VENDOR_UMC] = "UMC", 96 [X86_VENDOR_NEXGEN] = "NexGen", 97 [X86_VENDOR_CENTAUR] = "Centaur", 98 [X86_VENDOR_RISE] = "Rise", 99 [X86_VENDOR_TRANSMETA] = "Transmeta", 100 [X86_VENDOR_NSC] = "NSC", 101 [X86_VENDOR_SIS] = "SiS", 102 }; 103 104 static void load_ds(u32 segment) 105 { 106 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 107 } 108 109 static void load_es(u32 segment) 110 { 111 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 112 } 113 114 static void load_fs(u32 segment) 115 { 116 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 117 } 118 119 static void load_gs(u32 segment) 120 { 121 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 122 } 123 124 static void load_ss(u32 segment) 125 { 126 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 127 } 128 129 static void load_gdt(const u64 *boot_gdt, u16 num_entries) 130 { 131 struct gdt_ptr gdt; 132 133 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; 134 gdt.ptr = (u32)boot_gdt; 135 136 asm volatile("lgdtl %0\n" : : "m" (gdt)); 137 } 138 139 void setup_gdt(gd_t *new_gd, u64 *gdt_addr) 140 { 141 gdt_addr = new_gd->arch.gdt; 142 143 /* CS: code, read/execute, 4 GB, base 0 */ 144 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); 145 146 /* DS: data, read/write, 4 GB, base 0 */ 147 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); 148 149 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ 150 new_gd->arch.gd_addr = new_gd; 151 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, 152 (ulong)&new_gd->arch.gd_addr, 0xfffff); 153 154 /* 16-bit CS: code, read/execute, 64 kB, base 0 */ 155 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); 156 157 /* 16-bit DS: data, read/write, 64 kB, base 0 */ 158 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); 159 160 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); 161 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); 162 163 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); 164 load_ds(X86_GDT_ENTRY_32BIT_DS); 165 load_es(X86_GDT_ENTRY_32BIT_DS); 166 load_gs(X86_GDT_ENTRY_32BIT_DS); 167 load_ss(X86_GDT_ENTRY_32BIT_DS); 168 load_fs(X86_GDT_ENTRY_32BIT_FS); 169 } 170 171 #ifdef CONFIG_HAVE_FSP 172 /* 173 * Setup FSP execution environment GDT 174 * 175 * Per Intel FSP external architecture specification, before calling any FSP 176 * APIs, we need make sure the system is in flat 32-bit mode and both the code 177 * and data selectors should have full 4GB access range. Here we reuse the one 178 * we used in arch/x86/cpu/start16.S, and reload the segement registers. 179 */ 180 void setup_fsp_gdt(void) 181 { 182 load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4); 183 load_ds(X86_GDT_ENTRY_32BIT_DS); 184 load_ss(X86_GDT_ENTRY_32BIT_DS); 185 load_es(X86_GDT_ENTRY_32BIT_DS); 186 load_fs(X86_GDT_ENTRY_32BIT_DS); 187 load_gs(X86_GDT_ENTRY_32BIT_DS); 188 } 189 #endif 190 191 int __weak x86_cleanup_before_linux(void) 192 { 193 #ifdef CONFIG_BOOTSTAGE_STASH 194 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, 195 CONFIG_BOOTSTAGE_STASH_SIZE); 196 #endif 197 198 return 0; 199 } 200 201 /* 202 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected 203 * by the fact that they preserve the flags across the division of 5/2. 204 * PII and PPro exhibit this behavior too, but they have cpuid available. 205 */ 206 207 /* 208 * Perform the Cyrix 5/2 test. A Cyrix won't change 209 * the flags, while other 486 chips will. 210 */ 211 static inline int test_cyrix_52div(void) 212 { 213 unsigned int test; 214 215 __asm__ __volatile__( 216 "sahf\n\t" /* clear flags (%eax = 0x0005) */ 217 "div %b2\n\t" /* divide 5 by 2 */ 218 "lahf" /* store flags into %ah */ 219 : "=a" (test) 220 : "0" (5), "q" (2) 221 : "cc"); 222 223 /* AH is 0x02 on Cyrix after the divide.. */ 224 return (unsigned char) (test >> 8) == 0x02; 225 } 226 227 /* 228 * Detect a NexGen CPU running without BIOS hypercode new enough 229 * to have CPUID. (Thanks to Herbert Oppmann) 230 */ 231 232 static int deep_magic_nexgen_probe(void) 233 { 234 int ret; 235 236 __asm__ __volatile__ ( 237 " movw $0x5555, %%ax\n" 238 " xorw %%dx,%%dx\n" 239 " movw $2, %%cx\n" 240 " divw %%cx\n" 241 " movl $0, %%eax\n" 242 " jnz 1f\n" 243 " movl $1, %%eax\n" 244 "1:\n" 245 : "=a" (ret) : : "cx", "dx"); 246 return ret; 247 } 248 249 static bool has_cpuid(void) 250 { 251 return flag_is_changeable_p(X86_EFLAGS_ID); 252 } 253 254 static bool has_mtrr(void) 255 { 256 return cpuid_edx(0x00000001) & (1 << 12) ? true : false; 257 } 258 259 static int build_vendor_name(char *vendor_name) 260 { 261 struct cpuid_result result; 262 result = cpuid(0x00000000); 263 unsigned int *name_as_ints = (unsigned int *)vendor_name; 264 265 name_as_ints[0] = result.ebx; 266 name_as_ints[1] = result.edx; 267 name_as_ints[2] = result.ecx; 268 269 return result.eax; 270 } 271 272 static void identify_cpu(struct cpu_device_id *cpu) 273 { 274 char vendor_name[16]; 275 int i; 276 277 vendor_name[0] = '\0'; /* Unset */ 278 cpu->device = 0; /* fix gcc 4.4.4 warning */ 279 280 /* Find the id and vendor_name */ 281 if (!has_cpuid()) { 282 /* Its a 486 if we can modify the AC flag */ 283 if (flag_is_changeable_p(X86_EFLAGS_AC)) 284 cpu->device = 0x00000400; /* 486 */ 285 else 286 cpu->device = 0x00000300; /* 386 */ 287 if ((cpu->device == 0x00000400) && test_cyrix_52div()) { 288 memcpy(vendor_name, "CyrixInstead", 13); 289 /* If we ever care we can enable cpuid here */ 290 } 291 /* Detect NexGen with old hypercode */ 292 else if (deep_magic_nexgen_probe()) 293 memcpy(vendor_name, "NexGenDriven", 13); 294 } 295 if (has_cpuid()) { 296 int cpuid_level; 297 298 cpuid_level = build_vendor_name(vendor_name); 299 vendor_name[12] = '\0'; 300 301 /* Intel-defined flags: level 0x00000001 */ 302 if (cpuid_level >= 0x00000001) { 303 cpu->device = cpuid_eax(0x00000001); 304 } else { 305 /* Have CPUID level 0 only unheard of */ 306 cpu->device = 0x00000400; 307 } 308 } 309 cpu->vendor = X86_VENDOR_UNKNOWN; 310 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { 311 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { 312 cpu->vendor = x86_vendors[i].vendor; 313 break; 314 } 315 } 316 } 317 318 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) 319 { 320 c->x86 = (tfms >> 8) & 0xf; 321 c->x86_model = (tfms >> 4) & 0xf; 322 c->x86_mask = tfms & 0xf; 323 if (c->x86 == 0xf) 324 c->x86 += (tfms >> 20) & 0xff; 325 if (c->x86 >= 0x6) 326 c->x86_model += ((tfms >> 16) & 0xF) << 4; 327 } 328 329 int x86_cpu_init_f(void) 330 { 331 const u32 em_rst = ~X86_CR0_EM; 332 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; 333 334 if (ll_boot_init()) { 335 /* initialize FPU, reset EM, set MP and NE */ 336 asm ("fninit\n" \ 337 "movl %%cr0, %%eax\n" \ 338 "andl %0, %%eax\n" \ 339 "orl %1, %%eax\n" \ 340 "movl %%eax, %%cr0\n" \ 341 : : "i" (em_rst), "i" (mp_ne_set) : "eax"); 342 } 343 344 /* identify CPU via cpuid and store the decoded info into gd->arch */ 345 if (has_cpuid()) { 346 struct cpu_device_id cpu; 347 struct cpuinfo_x86 c; 348 349 identify_cpu(&cpu); 350 get_fms(&c, cpu.device); 351 gd->arch.x86 = c.x86; 352 gd->arch.x86_vendor = cpu.vendor; 353 gd->arch.x86_model = c.x86_model; 354 gd->arch.x86_mask = c.x86_mask; 355 gd->arch.x86_device = cpu.device; 356 357 gd->arch.has_mtrr = has_mtrr(); 358 } 359 /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */ 360 gd->pci_ram_top = 0x80000000U; 361 362 /* Configure fixed range MTRRs for some legacy regions */ 363 if (gd->arch.has_mtrr) { 364 u64 mtrr_cap; 365 366 mtrr_cap = native_read_msr(MTRR_CAP_MSR); 367 if (mtrr_cap & MTRR_CAP_FIX) { 368 /* Mark the VGA RAM area as uncacheable */ 369 native_write_msr(MTRR_FIX_16K_A0000_MSR, 370 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE), 371 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); 372 373 /* 374 * Mark the PCI ROM area as cacheable to improve ROM 375 * execution performance. 376 */ 377 native_write_msr(MTRR_FIX_4K_C0000_MSR, 378 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 379 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 380 native_write_msr(MTRR_FIX_4K_C8000_MSR, 381 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 382 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 383 native_write_msr(MTRR_FIX_4K_D0000_MSR, 384 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 385 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 386 native_write_msr(MTRR_FIX_4K_D8000_MSR, 387 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), 388 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 389 390 /* Enable the fixed range MTRRs */ 391 msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); 392 } 393 } 394 395 return 0; 396 } 397 398 void x86_enable_caches(void) 399 { 400 unsigned long cr0; 401 402 cr0 = read_cr0(); 403 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); 404 write_cr0(cr0); 405 wbinvd(); 406 } 407 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); 408 409 void x86_disable_caches(void) 410 { 411 unsigned long cr0; 412 413 cr0 = read_cr0(); 414 cr0 |= X86_CR0_NW | X86_CR0_CD; 415 wbinvd(); 416 write_cr0(cr0); 417 wbinvd(); 418 } 419 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); 420 421 int x86_init_cache(void) 422 { 423 enable_caches(); 424 425 return 0; 426 } 427 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 428 429 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 430 { 431 printf("resetting ...\n"); 432 433 /* wait 50 ms */ 434 udelay(50000); 435 disable_interrupts(); 436 reset_cpu(0); 437 438 /*NOTREACHED*/ 439 return 0; 440 } 441 442 void flush_cache(unsigned long dummy1, unsigned long dummy2) 443 { 444 asm("wbinvd\n"); 445 } 446 447 __weak void reset_cpu(ulong addr) 448 { 449 /* Do a hard reset through the chipset's reset control register */ 450 outb(SYS_RST | RST_CPU, PORT_RESET); 451 for (;;) 452 cpu_hlt(); 453 } 454 455 void x86_full_reset(void) 456 { 457 outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET); 458 } 459 460 int dcache_status(void) 461 { 462 return !(read_cr0() & X86_CR0_CD); 463 } 464 465 /* Define these functions to allow ehch-hcd to function */ 466 void flush_dcache_range(unsigned long start, unsigned long stop) 467 { 468 } 469 470 void invalidate_dcache_range(unsigned long start, unsigned long stop) 471 { 472 } 473 474 void dcache_enable(void) 475 { 476 enable_caches(); 477 } 478 479 void dcache_disable(void) 480 { 481 disable_caches(); 482 } 483 484 void icache_enable(void) 485 { 486 } 487 488 void icache_disable(void) 489 { 490 } 491 492 int icache_status(void) 493 { 494 return 1; 495 } 496 497 void cpu_enable_paging_pae(ulong cr3) 498 { 499 __asm__ __volatile__( 500 /* Load the page table address */ 501 "movl %0, %%cr3\n" 502 /* Enable pae */ 503 "movl %%cr4, %%eax\n" 504 "orl $0x00000020, %%eax\n" 505 "movl %%eax, %%cr4\n" 506 /* Enable paging */ 507 "movl %%cr0, %%eax\n" 508 "orl $0x80000000, %%eax\n" 509 "movl %%eax, %%cr0\n" 510 : 511 : "r" (cr3) 512 : "eax"); 513 } 514 515 void cpu_disable_paging_pae(void) 516 { 517 /* Turn off paging */ 518 __asm__ __volatile__ ( 519 /* Disable paging */ 520 "movl %%cr0, %%eax\n" 521 "andl $0x7fffffff, %%eax\n" 522 "movl %%eax, %%cr0\n" 523 /* Disable pae */ 524 "movl %%cr4, %%eax\n" 525 "andl $0xffffffdf, %%eax\n" 526 "movl %%eax, %%cr4\n" 527 : 528 : 529 : "eax"); 530 } 531 532 static bool can_detect_long_mode(void) 533 { 534 return cpuid_eax(0x80000000) > 0x80000000UL; 535 } 536 537 static bool has_long_mode(void) 538 { 539 return cpuid_edx(0x80000001) & (1 << 29) ? true : false; 540 } 541 542 int cpu_has_64bit(void) 543 { 544 return has_cpuid() && can_detect_long_mode() && 545 has_long_mode(); 546 } 547 548 const char *cpu_vendor_name(int vendor) 549 { 550 const char *name; 551 name = "<invalid cpu vendor>"; 552 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && 553 (x86_vendor_name[vendor] != 0)) 554 name = x86_vendor_name[vendor]; 555 556 return name; 557 } 558 559 char *cpu_get_name(char *name) 560 { 561 unsigned int *name_as_ints = (unsigned int *)name; 562 struct cpuid_result regs; 563 char *ptr; 564 int i; 565 566 /* This bit adds up to 48 bytes */ 567 for (i = 0; i < 3; i++) { 568 regs = cpuid(0x80000002 + i); 569 name_as_ints[i * 4 + 0] = regs.eax; 570 name_as_ints[i * 4 + 1] = regs.ebx; 571 name_as_ints[i * 4 + 2] = regs.ecx; 572 name_as_ints[i * 4 + 3] = regs.edx; 573 } 574 name[CPU_MAX_NAME_LEN - 1] = '\0'; 575 576 /* Skip leading spaces. */ 577 ptr = name; 578 while (*ptr == ' ') 579 ptr++; 580 581 return ptr; 582 } 583 584 int default_print_cpuinfo(void) 585 { 586 printf("CPU: %s, vendor %s, device %xh\n", 587 cpu_has_64bit() ? "x86_64" : "x86", 588 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); 589 590 return 0; 591 } 592 593 #define PAGETABLE_SIZE (6 * 4096) 594 595 /** 596 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode 597 * 598 * @pgtable: Pointer to a 24iKB block of memory 599 */ 600 static void build_pagetable(uint32_t *pgtable) 601 { 602 uint i; 603 604 memset(pgtable, '\0', PAGETABLE_SIZE); 605 606 /* Level 4 needs a single entry */ 607 pgtable[0] = (uint32_t)&pgtable[1024] + 7; 608 609 /* Level 3 has one 64-bit entry for each GiB of memory */ 610 for (i = 0; i < 4; i++) { 611 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + 612 0x1000 * i + 7; 613 } 614 615 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ 616 for (i = 0; i < 2048; i++) 617 pgtable[2048 + i * 2] = 0x183 + (i << 21UL); 618 } 619 620 int cpu_jump_to_64bit(ulong setup_base, ulong target) 621 { 622 uint32_t *pgtable; 623 624 pgtable = memalign(4096, PAGETABLE_SIZE); 625 if (!pgtable) 626 return -ENOMEM; 627 628 build_pagetable(pgtable); 629 cpu_call64((ulong)pgtable, setup_base, target); 630 free(pgtable); 631 632 return -EFAULT; 633 } 634 635 void show_boot_progress(int val) 636 { 637 #if MIN_PORT80_KCLOCKS_DELAY 638 /* 639 * Scale the time counter reading to avoid using 64 bit arithmetics. 640 * Can't use get_timer() here becuase it could be not yet 641 * initialized or even implemented. 642 */ 643 if (!gd->arch.tsc_prev) { 644 gd->arch.tsc_base_kclocks = rdtsc() / 1000; 645 gd->arch.tsc_prev = 0; 646 } else { 647 uint32_t now; 648 649 do { 650 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; 651 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); 652 gd->arch.tsc_prev = now; 653 } 654 #endif 655 outb(val, POST_PORT); 656 } 657 658 #ifndef CONFIG_SYS_COREBOOT 659 int last_stage_init(void) 660 { 661 write_tables(); 662 663 return 0; 664 } 665 #endif 666 667 #ifdef CONFIG_SMP 668 static int enable_smis(struct udevice *cpu, void *unused) 669 { 670 return 0; 671 } 672 673 static struct mp_flight_record mp_steps[] = { 674 MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL), 675 /* Wait for APs to finish initialization before proceeding */ 676 MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), 677 }; 678 679 static int x86_mp_init(void) 680 { 681 struct mp_params mp_params; 682 683 mp_params.parallel_microcode_load = 0, 684 mp_params.flight_plan = &mp_steps[0]; 685 mp_params.num_records = ARRAY_SIZE(mp_steps); 686 mp_params.microcode_pointer = 0; 687 688 if (mp_init(&mp_params)) { 689 printf("Warning: MP init failure\n"); 690 return -EIO; 691 } 692 693 return 0; 694 } 695 #endif 696 697 __weak int x86_init_cpus(void) 698 { 699 #ifdef CONFIG_SMP 700 debug("Init additional CPUs\n"); 701 x86_mp_init(); 702 #else 703 struct udevice *dev; 704 705 /* 706 * This causes the cpu-x86 driver to be probed. 707 * We don't check return value here as we want to allow boards 708 * which have not been converted to use cpu uclass driver to boot. 709 */ 710 uclass_first_device(UCLASS_CPU, &dev); 711 #endif 712 713 return 0; 714 } 715 716 int cpu_init_r(void) 717 { 718 if (ll_boot_init()) 719 return x86_init_cpus(); 720 721 return 0; 722 } 723