1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2008-2011 4 * Graeme Russ, <graeme.russ@gmail.com> 5 * 6 * (C) Copyright 2002 7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 8 * 9 * (C) Copyright 2002 10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 11 * Marius Groeger <mgroeger@sysgo.de> 12 * 13 * (C) Copyright 2002 14 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 15 * Alex Zuepke <azu@sysgo.de> 16 * 17 * Part of this file is adapted from coreboot 18 * src/arch/x86/lib/cpu.c 19 */ 20 21 #include <common.h> 22 #include <command.h> 23 #include <dm.h> 24 #include <errno.h> 25 #include <malloc.h> 26 #include <syscon.h> 27 #include <asm/acpi.h> 28 #include <asm/acpi_s3.h> 29 #include <asm/acpi_table.h> 30 #include <asm/control_regs.h> 31 #include <asm/coreboot_tables.h> 32 #include <asm/cpu.h> 33 #include <asm/lapic.h> 34 #include <asm/microcode.h> 35 #include <asm/mp.h> 36 #include <asm/mrccache.h> 37 #include <asm/msr.h> 38 #include <asm/mtrr.h> 39 #include <asm/post.h> 40 #include <asm/processor.h> 41 #include <asm/processor-flags.h> 42 #include <asm/interrupt.h> 43 #include <asm/tables.h> 44 #include <linux/compiler.h> 45 46 DECLARE_GLOBAL_DATA_PTR; 47 48 static const char *const x86_vendor_name[] = { 49 [X86_VENDOR_INTEL] = "Intel", 50 [X86_VENDOR_CYRIX] = "Cyrix", 51 [X86_VENDOR_AMD] = "AMD", 52 [X86_VENDOR_UMC] = "UMC", 53 [X86_VENDOR_NEXGEN] = "NexGen", 54 [X86_VENDOR_CENTAUR] = "Centaur", 55 [X86_VENDOR_RISE] = "Rise", 56 [X86_VENDOR_TRANSMETA] = "Transmeta", 57 [X86_VENDOR_NSC] = "NSC", 58 [X86_VENDOR_SIS] = "SiS", 59 }; 60 61 int __weak x86_cleanup_before_linux(void) 62 { 63 #ifdef CONFIG_BOOTSTAGE_STASH 64 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, 65 CONFIG_BOOTSTAGE_STASH_SIZE); 66 #endif 67 68 return 0; 69 } 70 71 int x86_init_cache(void) 72 { 73 enable_caches(); 74 75 return 0; 76 } 77 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 78 79 void flush_cache(unsigned long dummy1, unsigned long dummy2) 80 { 81 asm("wbinvd\n"); 82 } 83 84 /* Define these functions to allow ehch-hcd to function */ 85 void flush_dcache_range(unsigned long start, unsigned long stop) 86 { 87 } 88 89 void invalidate_dcache_range(unsigned long start, unsigned long stop) 90 { 91 } 92 93 void dcache_enable(void) 94 { 95 enable_caches(); 96 } 97 98 void dcache_disable(void) 99 { 100 disable_caches(); 101 } 102 103 void icache_enable(void) 104 { 105 } 106 107 void icache_disable(void) 108 { 109 } 110 111 int icache_status(void) 112 { 113 return 1; 114 } 115 116 const char *cpu_vendor_name(int vendor) 117 { 118 const char *name; 119 name = "<invalid cpu vendor>"; 120 if (vendor < ARRAY_SIZE(x86_vendor_name) && 121 x86_vendor_name[vendor]) 122 name = x86_vendor_name[vendor]; 123 124 return name; 125 } 126 127 char *cpu_get_name(char *name) 128 { 129 unsigned int *name_as_ints = (unsigned int *)name; 130 struct cpuid_result regs; 131 char *ptr; 132 int i; 133 134 /* This bit adds up to 48 bytes */ 135 for (i = 0; i < 3; i++) { 136 regs = cpuid(0x80000002 + i); 137 name_as_ints[i * 4 + 0] = regs.eax; 138 name_as_ints[i * 4 + 1] = regs.ebx; 139 name_as_ints[i * 4 + 2] = regs.ecx; 140 name_as_ints[i * 4 + 3] = regs.edx; 141 } 142 name[CPU_MAX_NAME_LEN - 1] = '\0'; 143 144 /* Skip leading spaces. */ 145 ptr = name; 146 while (*ptr == ' ') 147 ptr++; 148 149 return ptr; 150 } 151 152 int default_print_cpuinfo(void) 153 { 154 printf("CPU: %s, vendor %s, device %xh\n", 155 cpu_has_64bit() ? "x86_64" : "x86", 156 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); 157 158 #ifdef CONFIG_HAVE_ACPI_RESUME 159 debug("ACPI previous sleep state: %s\n", 160 acpi_ss_string(gd->arch.prev_sleep_state)); 161 #endif 162 163 return 0; 164 } 165 166 void show_boot_progress(int val) 167 { 168 outb(val, POST_PORT); 169 } 170 171 #if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB) 172 /* 173 * Implement a weak default function for boards that optionally 174 * need to clean up the system before jumping to the kernel. 175 */ 176 __weak void board_final_cleanup(void) 177 { 178 } 179 180 int last_stage_init(void) 181 { 182 struct acpi_fadt __maybe_unused *fadt; 183 184 board_final_cleanup(); 185 186 #ifdef CONFIG_HAVE_ACPI_RESUME 187 fadt = acpi_find_fadt(); 188 189 if (fadt && gd->arch.prev_sleep_state == ACPI_S3) 190 acpi_resume(fadt); 191 #endif 192 193 write_tables(); 194 195 #ifdef CONFIG_GENERATE_ACPI_TABLE 196 fadt = acpi_find_fadt(); 197 198 /* Don't touch ACPI hardware on HW reduced platforms */ 199 if (fadt && !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)) { 200 /* 201 * Other than waiting for OSPM to request us to switch to ACPI 202 * mode, do it by ourselves, since SMI will not be triggered. 203 */ 204 enter_acpi_mode(fadt->pm1a_cnt_blk); 205 } 206 #endif 207 208 return 0; 209 } 210 #endif 211 212 static int x86_init_cpus(void) 213 { 214 #ifdef CONFIG_SMP 215 debug("Init additional CPUs\n"); 216 x86_mp_init(); 217 #else 218 struct udevice *dev; 219 220 /* 221 * This causes the cpu-x86 driver to be probed. 222 * We don't check return value here as we want to allow boards 223 * which have not been converted to use cpu uclass driver to boot. 224 */ 225 uclass_first_device(UCLASS_CPU, &dev); 226 #endif 227 228 return 0; 229 } 230 231 int cpu_init_r(void) 232 { 233 struct udevice *dev; 234 int ret; 235 236 if (!ll_boot_init()) 237 return 0; 238 239 ret = x86_init_cpus(); 240 if (ret) 241 return ret; 242 243 /* 244 * Set up the northbridge, PCH and LPC if available. Note that these 245 * may have had some limited pre-relocation init if they were probed 246 * before relocation, but this is post relocation. 247 */ 248 uclass_first_device(UCLASS_NORTHBRIDGE, &dev); 249 uclass_first_device(UCLASS_PCH, &dev); 250 uclass_first_device(UCLASS_LPC, &dev); 251 252 /* Set up pin control if available */ 253 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev); 254 debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret); 255 256 return 0; 257 } 258 259 #ifndef CONFIG_EFI_STUB 260 int reserve_arch(void) 261 { 262 #ifdef CONFIG_ENABLE_MRC_CACHE 263 mrccache_reserve(); 264 #endif 265 266 #ifdef CONFIG_SEABIOS 267 high_table_reserve(); 268 #endif 269 270 #ifdef CONFIG_HAVE_ACPI_RESUME 271 acpi_s3_reserve(); 272 273 #ifdef CONFIG_HAVE_FSP 274 /* 275 * Save stack address to CMOS so that at next S3 boot, 276 * we can use it as the stack address for fsp_contiue() 277 */ 278 fsp_save_s3_stack(); 279 #endif /* CONFIG_HAVE_FSP */ 280 #endif /* CONFIG_HAVE_ACPI_RESUME */ 281 282 return 0; 283 } 284 #endif 285