1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * Part of this file is adapted from coreboot 17 * src/arch/x86/lib/cpu.c 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22 #include <common.h> 23 #include <command.h> 24 #include <dm.h> 25 #include <errno.h> 26 #include <malloc.h> 27 #include <syscon.h> 28 #include <asm/control_regs.h> 29 #include <asm/coreboot_tables.h> 30 #include <asm/cpu.h> 31 #include <asm/lapic.h> 32 #include <asm/microcode.h> 33 #include <asm/mp.h> 34 #include <asm/mrccache.h> 35 #include <asm/msr.h> 36 #include <asm/mtrr.h> 37 #include <asm/post.h> 38 #include <asm/processor.h> 39 #include <asm/processor-flags.h> 40 #include <asm/interrupt.h> 41 #include <asm/tables.h> 42 #include <linux/compiler.h> 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 static const char *const x86_vendor_name[] = { 47 [X86_VENDOR_INTEL] = "Intel", 48 [X86_VENDOR_CYRIX] = "Cyrix", 49 [X86_VENDOR_AMD] = "AMD", 50 [X86_VENDOR_UMC] = "UMC", 51 [X86_VENDOR_NEXGEN] = "NexGen", 52 [X86_VENDOR_CENTAUR] = "Centaur", 53 [X86_VENDOR_RISE] = "Rise", 54 [X86_VENDOR_TRANSMETA] = "Transmeta", 55 [X86_VENDOR_NSC] = "NSC", 56 [X86_VENDOR_SIS] = "SiS", 57 }; 58 59 int __weak x86_cleanup_before_linux(void) 60 { 61 #ifdef CONFIG_BOOTSTAGE_STASH 62 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, 63 CONFIG_BOOTSTAGE_STASH_SIZE); 64 #endif 65 66 return 0; 67 } 68 69 int x86_init_cache(void) 70 { 71 enable_caches(); 72 73 return 0; 74 } 75 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 76 77 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 78 { 79 printf("resetting ...\n"); 80 81 /* wait 50 ms */ 82 udelay(50000); 83 disable_interrupts(); 84 reset_cpu(0); 85 86 /*NOTREACHED*/ 87 return 0; 88 } 89 90 void flush_cache(unsigned long dummy1, unsigned long dummy2) 91 { 92 asm("wbinvd\n"); 93 } 94 95 __weak void reset_cpu(ulong addr) 96 { 97 /* Do a hard reset through the chipset's reset control register */ 98 outb(SYS_RST | RST_CPU, IO_PORT_RESET); 99 for (;;) 100 cpu_hlt(); 101 } 102 103 void x86_full_reset(void) 104 { 105 outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET); 106 } 107 108 /* Define these functions to allow ehch-hcd to function */ 109 void flush_dcache_range(unsigned long start, unsigned long stop) 110 { 111 } 112 113 void invalidate_dcache_range(unsigned long start, unsigned long stop) 114 { 115 } 116 117 void dcache_enable(void) 118 { 119 enable_caches(); 120 } 121 122 void dcache_disable(void) 123 { 124 disable_caches(); 125 } 126 127 void icache_enable(void) 128 { 129 } 130 131 void icache_disable(void) 132 { 133 } 134 135 int icache_status(void) 136 { 137 return 1; 138 } 139 140 const char *cpu_vendor_name(int vendor) 141 { 142 const char *name; 143 name = "<invalid cpu vendor>"; 144 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && 145 (x86_vendor_name[vendor] != 0)) 146 name = x86_vendor_name[vendor]; 147 148 return name; 149 } 150 151 char *cpu_get_name(char *name) 152 { 153 unsigned int *name_as_ints = (unsigned int *)name; 154 struct cpuid_result regs; 155 char *ptr; 156 int i; 157 158 /* This bit adds up to 48 bytes */ 159 for (i = 0; i < 3; i++) { 160 regs = cpuid(0x80000002 + i); 161 name_as_ints[i * 4 + 0] = regs.eax; 162 name_as_ints[i * 4 + 1] = regs.ebx; 163 name_as_ints[i * 4 + 2] = regs.ecx; 164 name_as_ints[i * 4 + 3] = regs.edx; 165 } 166 name[CPU_MAX_NAME_LEN - 1] = '\0'; 167 168 /* Skip leading spaces. */ 169 ptr = name; 170 while (*ptr == ' ') 171 ptr++; 172 173 return ptr; 174 } 175 176 int default_print_cpuinfo(void) 177 { 178 printf("CPU: %s, vendor %s, device %xh\n", 179 cpu_has_64bit() ? "x86_64" : "x86", 180 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); 181 182 return 0; 183 } 184 185 void show_boot_progress(int val) 186 { 187 outb(val, POST_PORT); 188 } 189 190 #ifndef CONFIG_SYS_COREBOOT 191 /* 192 * Implement a weak default function for boards that optionally 193 * need to clean up the system before jumping to the kernel. 194 */ 195 __weak void board_final_cleanup(void) 196 { 197 } 198 199 int last_stage_init(void) 200 { 201 write_tables(); 202 203 board_final_cleanup(); 204 205 return 0; 206 } 207 #endif 208 209 static int x86_init_cpus(void) 210 { 211 #ifdef CONFIG_SMP 212 debug("Init additional CPUs\n"); 213 x86_mp_init(); 214 #else 215 struct udevice *dev; 216 217 /* 218 * This causes the cpu-x86 driver to be probed. 219 * We don't check return value here as we want to allow boards 220 * which have not been converted to use cpu uclass driver to boot. 221 */ 222 uclass_first_device(UCLASS_CPU, &dev); 223 #endif 224 225 return 0; 226 } 227 228 int cpu_init_r(void) 229 { 230 struct udevice *dev; 231 int ret; 232 233 if (!ll_boot_init()) 234 return 0; 235 236 ret = x86_init_cpus(); 237 if (ret) 238 return ret; 239 240 /* 241 * Set up the northbridge, PCH and LPC if available. Note that these 242 * may have had some limited pre-relocation init if they were probed 243 * before relocation, but this is post relocation. 244 */ 245 uclass_first_device(UCLASS_NORTHBRIDGE, &dev); 246 uclass_first_device(UCLASS_PCH, &dev); 247 uclass_first_device(UCLASS_LPC, &dev); 248 249 /* Set up pin control if available */ 250 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev); 251 debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret); 252 253 return 0; 254 } 255 256 #ifndef CONFIG_EFI_STUB 257 int reserve_arch(void) 258 { 259 #ifdef CONFIG_ENABLE_MRC_CACHE 260 mrccache_reserve(); 261 #endif 262 263 #ifdef CONFIG_SEABIOS 264 high_table_reserve(); 265 #endif 266 267 return 0; 268 } 269 #endif 270