1 /* 2 * (C) Copyright 2008-2011 3 * Graeme Russ, <graeme.russ@gmail.com> 4 * 5 * (C) Copyright 2002 6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 7 * 8 * (C) Copyright 2002 9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 10 * Marius Groeger <mgroeger@sysgo.de> 11 * 12 * (C) Copyright 2002 13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 14 * Alex Zuepke <azu@sysgo.de> 15 * 16 * Part of this file is adapted from coreboot 17 * src/arch/x86/lib/cpu.c 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22 #include <common.h> 23 #include <command.h> 24 #include <cpu.h> 25 #include <dm.h> 26 #include <errno.h> 27 #include <malloc.h> 28 #include <asm/control_regs.h> 29 #include <asm/cpu.h> 30 #include <asm/post.h> 31 #include <asm/processor.h> 32 #include <asm/processor-flags.h> 33 #include <asm/interrupt.h> 34 #include <asm/tables.h> 35 #include <linux/compiler.h> 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Constructor for a conventional segment GDT (or LDT) entry 41 * This is a macro so it can be used in initialisers 42 */ 43 #define GDT_ENTRY(flags, base, limit) \ 44 ((((base) & 0xff000000ULL) << (56-24)) | \ 45 (((flags) & 0x0000f0ffULL) << 40) | \ 46 (((limit) & 0x000f0000ULL) << (48-16)) | \ 47 (((base) & 0x00ffffffULL) << 16) | \ 48 (((limit) & 0x0000ffffULL))) 49 50 struct gdt_ptr { 51 u16 len; 52 u32 ptr; 53 } __packed; 54 55 struct cpu_device_id { 56 unsigned vendor; 57 unsigned device; 58 }; 59 60 struct cpuinfo_x86 { 61 uint8_t x86; /* CPU family */ 62 uint8_t x86_vendor; /* CPU vendor */ 63 uint8_t x86_model; 64 uint8_t x86_mask; 65 }; 66 67 /* 68 * List of cpu vendor strings along with their normalized 69 * id values. 70 */ 71 static struct { 72 int vendor; 73 const char *name; 74 } x86_vendors[] = { 75 { X86_VENDOR_INTEL, "GenuineIntel", }, 76 { X86_VENDOR_CYRIX, "CyrixInstead", }, 77 { X86_VENDOR_AMD, "AuthenticAMD", }, 78 { X86_VENDOR_UMC, "UMC UMC UMC ", }, 79 { X86_VENDOR_NEXGEN, "NexGenDriven", }, 80 { X86_VENDOR_CENTAUR, "CentaurHauls", }, 81 { X86_VENDOR_RISE, "RiseRiseRise", }, 82 { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, 83 { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, 84 { X86_VENDOR_NSC, "Geode by NSC", }, 85 { X86_VENDOR_SIS, "SiS SiS SiS ", }, 86 }; 87 88 static const char *const x86_vendor_name[] = { 89 [X86_VENDOR_INTEL] = "Intel", 90 [X86_VENDOR_CYRIX] = "Cyrix", 91 [X86_VENDOR_AMD] = "AMD", 92 [X86_VENDOR_UMC] = "UMC", 93 [X86_VENDOR_NEXGEN] = "NexGen", 94 [X86_VENDOR_CENTAUR] = "Centaur", 95 [X86_VENDOR_RISE] = "Rise", 96 [X86_VENDOR_TRANSMETA] = "Transmeta", 97 [X86_VENDOR_NSC] = "NSC", 98 [X86_VENDOR_SIS] = "SiS", 99 }; 100 101 static void load_ds(u32 segment) 102 { 103 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 104 } 105 106 static void load_es(u32 segment) 107 { 108 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 109 } 110 111 static void load_fs(u32 segment) 112 { 113 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 114 } 115 116 static void load_gs(u32 segment) 117 { 118 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 119 } 120 121 static void load_ss(u32 segment) 122 { 123 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); 124 } 125 126 static void load_gdt(const u64 *boot_gdt, u16 num_entries) 127 { 128 struct gdt_ptr gdt; 129 130 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; 131 gdt.ptr = (u32)boot_gdt; 132 133 asm volatile("lgdtl %0\n" : : "m" (gdt)); 134 } 135 136 void setup_gdt(gd_t *id, u64 *gdt_addr) 137 { 138 id->arch.gdt = gdt_addr; 139 /* CS: code, read/execute, 4 GB, base 0 */ 140 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); 141 142 /* DS: data, read/write, 4 GB, base 0 */ 143 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); 144 145 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ 146 id->arch.gd_addr = id; 147 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, 148 (ulong)&id->arch.gd_addr, 0xfffff); 149 150 /* 16-bit CS: code, read/execute, 64 kB, base 0 */ 151 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); 152 153 /* 16-bit DS: data, read/write, 64 kB, base 0 */ 154 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); 155 156 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); 157 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); 158 159 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); 160 load_ds(X86_GDT_ENTRY_32BIT_DS); 161 load_es(X86_GDT_ENTRY_32BIT_DS); 162 load_gs(X86_GDT_ENTRY_32BIT_DS); 163 load_ss(X86_GDT_ENTRY_32BIT_DS); 164 load_fs(X86_GDT_ENTRY_32BIT_FS); 165 } 166 167 #ifdef CONFIG_HAVE_FSP 168 /* 169 * Setup FSP execution environment GDT 170 * 171 * Per Intel FSP external architecture specification, before calling any FSP 172 * APIs, we need make sure the system is in flat 32-bit mode and both the code 173 * and data selectors should have full 4GB access range. Here we reuse the one 174 * we used in arch/x86/cpu/start16.S, and reload the segement registers. 175 */ 176 void setup_fsp_gdt(void) 177 { 178 load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4); 179 load_ds(X86_GDT_ENTRY_32BIT_DS); 180 load_ss(X86_GDT_ENTRY_32BIT_DS); 181 load_es(X86_GDT_ENTRY_32BIT_DS); 182 load_fs(X86_GDT_ENTRY_32BIT_DS); 183 load_gs(X86_GDT_ENTRY_32BIT_DS); 184 } 185 #endif 186 187 int __weak x86_cleanup_before_linux(void) 188 { 189 #ifdef CONFIG_BOOTSTAGE_STASH 190 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, 191 CONFIG_BOOTSTAGE_STASH_SIZE); 192 #endif 193 194 return 0; 195 } 196 197 /* 198 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected 199 * by the fact that they preserve the flags across the division of 5/2. 200 * PII and PPro exhibit this behavior too, but they have cpuid available. 201 */ 202 203 /* 204 * Perform the Cyrix 5/2 test. A Cyrix won't change 205 * the flags, while other 486 chips will. 206 */ 207 static inline int test_cyrix_52div(void) 208 { 209 unsigned int test; 210 211 __asm__ __volatile__( 212 "sahf\n\t" /* clear flags (%eax = 0x0005) */ 213 "div %b2\n\t" /* divide 5 by 2 */ 214 "lahf" /* store flags into %ah */ 215 : "=a" (test) 216 : "0" (5), "q" (2) 217 : "cc"); 218 219 /* AH is 0x02 on Cyrix after the divide.. */ 220 return (unsigned char) (test >> 8) == 0x02; 221 } 222 223 /* 224 * Detect a NexGen CPU running without BIOS hypercode new enough 225 * to have CPUID. (Thanks to Herbert Oppmann) 226 */ 227 228 static int deep_magic_nexgen_probe(void) 229 { 230 int ret; 231 232 __asm__ __volatile__ ( 233 " movw $0x5555, %%ax\n" 234 " xorw %%dx,%%dx\n" 235 " movw $2, %%cx\n" 236 " divw %%cx\n" 237 " movl $0, %%eax\n" 238 " jnz 1f\n" 239 " movl $1, %%eax\n" 240 "1:\n" 241 : "=a" (ret) : : "cx", "dx"); 242 return ret; 243 } 244 245 static bool has_cpuid(void) 246 { 247 return flag_is_changeable_p(X86_EFLAGS_ID); 248 } 249 250 static bool has_mtrr(void) 251 { 252 return cpuid_edx(0x00000001) & (1 << 12) ? true : false; 253 } 254 255 static int build_vendor_name(char *vendor_name) 256 { 257 struct cpuid_result result; 258 result = cpuid(0x00000000); 259 unsigned int *name_as_ints = (unsigned int *)vendor_name; 260 261 name_as_ints[0] = result.ebx; 262 name_as_ints[1] = result.edx; 263 name_as_ints[2] = result.ecx; 264 265 return result.eax; 266 } 267 268 static void identify_cpu(struct cpu_device_id *cpu) 269 { 270 char vendor_name[16]; 271 int i; 272 273 vendor_name[0] = '\0'; /* Unset */ 274 cpu->device = 0; /* fix gcc 4.4.4 warning */ 275 276 /* Find the id and vendor_name */ 277 if (!has_cpuid()) { 278 /* Its a 486 if we can modify the AC flag */ 279 if (flag_is_changeable_p(X86_EFLAGS_AC)) 280 cpu->device = 0x00000400; /* 486 */ 281 else 282 cpu->device = 0x00000300; /* 386 */ 283 if ((cpu->device == 0x00000400) && test_cyrix_52div()) { 284 memcpy(vendor_name, "CyrixInstead", 13); 285 /* If we ever care we can enable cpuid here */ 286 } 287 /* Detect NexGen with old hypercode */ 288 else if (deep_magic_nexgen_probe()) 289 memcpy(vendor_name, "NexGenDriven", 13); 290 } 291 if (has_cpuid()) { 292 int cpuid_level; 293 294 cpuid_level = build_vendor_name(vendor_name); 295 vendor_name[12] = '\0'; 296 297 /* Intel-defined flags: level 0x00000001 */ 298 if (cpuid_level >= 0x00000001) { 299 cpu->device = cpuid_eax(0x00000001); 300 } else { 301 /* Have CPUID level 0 only unheard of */ 302 cpu->device = 0x00000400; 303 } 304 } 305 cpu->vendor = X86_VENDOR_UNKNOWN; 306 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { 307 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { 308 cpu->vendor = x86_vendors[i].vendor; 309 break; 310 } 311 } 312 } 313 314 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) 315 { 316 c->x86 = (tfms >> 8) & 0xf; 317 c->x86_model = (tfms >> 4) & 0xf; 318 c->x86_mask = tfms & 0xf; 319 if (c->x86 == 0xf) 320 c->x86 += (tfms >> 20) & 0xff; 321 if (c->x86 >= 0x6) 322 c->x86_model += ((tfms >> 16) & 0xF) << 4; 323 } 324 325 int x86_cpu_init_f(void) 326 { 327 const u32 em_rst = ~X86_CR0_EM; 328 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; 329 330 /* initialize FPU, reset EM, set MP and NE */ 331 asm ("fninit\n" \ 332 "movl %%cr0, %%eax\n" \ 333 "andl %0, %%eax\n" \ 334 "orl %1, %%eax\n" \ 335 "movl %%eax, %%cr0\n" \ 336 : : "i" (em_rst), "i" (mp_ne_set) : "eax"); 337 338 /* identify CPU via cpuid and store the decoded info into gd->arch */ 339 if (has_cpuid()) { 340 struct cpu_device_id cpu; 341 struct cpuinfo_x86 c; 342 343 identify_cpu(&cpu); 344 get_fms(&c, cpu.device); 345 gd->arch.x86 = c.x86; 346 gd->arch.x86_vendor = cpu.vendor; 347 gd->arch.x86_model = c.x86_model; 348 gd->arch.x86_mask = c.x86_mask; 349 gd->arch.x86_device = cpu.device; 350 351 gd->arch.has_mtrr = has_mtrr(); 352 } 353 354 return 0; 355 } 356 357 void x86_enable_caches(void) 358 { 359 unsigned long cr0; 360 361 cr0 = read_cr0(); 362 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); 363 write_cr0(cr0); 364 wbinvd(); 365 } 366 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); 367 368 void x86_disable_caches(void) 369 { 370 unsigned long cr0; 371 372 cr0 = read_cr0(); 373 cr0 |= X86_CR0_NW | X86_CR0_CD; 374 wbinvd(); 375 write_cr0(cr0); 376 wbinvd(); 377 } 378 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); 379 380 int x86_init_cache(void) 381 { 382 enable_caches(); 383 384 return 0; 385 } 386 int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); 387 388 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 389 { 390 printf("resetting ...\n"); 391 392 /* wait 50 ms */ 393 udelay(50000); 394 disable_interrupts(); 395 reset_cpu(0); 396 397 /*NOTREACHED*/ 398 return 0; 399 } 400 401 void flush_cache(unsigned long dummy1, unsigned long dummy2) 402 { 403 asm("wbinvd\n"); 404 } 405 406 __weak void reset_cpu(ulong addr) 407 { 408 /* Do a hard reset through the chipset's reset control register */ 409 outb(SYS_RST | RST_CPU, PORT_RESET); 410 for (;;) 411 cpu_hlt(); 412 } 413 414 void x86_full_reset(void) 415 { 416 outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET); 417 } 418 419 int dcache_status(void) 420 { 421 return !(read_cr0() & 0x40000000); 422 } 423 424 /* Define these functions to allow ehch-hcd to function */ 425 void flush_dcache_range(unsigned long start, unsigned long stop) 426 { 427 } 428 429 void invalidate_dcache_range(unsigned long start, unsigned long stop) 430 { 431 } 432 433 void dcache_enable(void) 434 { 435 enable_caches(); 436 } 437 438 void dcache_disable(void) 439 { 440 disable_caches(); 441 } 442 443 void icache_enable(void) 444 { 445 } 446 447 void icache_disable(void) 448 { 449 } 450 451 int icache_status(void) 452 { 453 return 1; 454 } 455 456 void cpu_enable_paging_pae(ulong cr3) 457 { 458 __asm__ __volatile__( 459 /* Load the page table address */ 460 "movl %0, %%cr3\n" 461 /* Enable pae */ 462 "movl %%cr4, %%eax\n" 463 "orl $0x00000020, %%eax\n" 464 "movl %%eax, %%cr4\n" 465 /* Enable paging */ 466 "movl %%cr0, %%eax\n" 467 "orl $0x80000000, %%eax\n" 468 "movl %%eax, %%cr0\n" 469 : 470 : "r" (cr3) 471 : "eax"); 472 } 473 474 void cpu_disable_paging_pae(void) 475 { 476 /* Turn off paging */ 477 __asm__ __volatile__ ( 478 /* Disable paging */ 479 "movl %%cr0, %%eax\n" 480 "andl $0x7fffffff, %%eax\n" 481 "movl %%eax, %%cr0\n" 482 /* Disable pae */ 483 "movl %%cr4, %%eax\n" 484 "andl $0xffffffdf, %%eax\n" 485 "movl %%eax, %%cr4\n" 486 : 487 : 488 : "eax"); 489 } 490 491 static bool can_detect_long_mode(void) 492 { 493 return cpuid_eax(0x80000000) > 0x80000000UL; 494 } 495 496 static bool has_long_mode(void) 497 { 498 return cpuid_edx(0x80000001) & (1 << 29) ? true : false; 499 } 500 501 int cpu_has_64bit(void) 502 { 503 return has_cpuid() && can_detect_long_mode() && 504 has_long_mode(); 505 } 506 507 const char *cpu_vendor_name(int vendor) 508 { 509 const char *name; 510 name = "<invalid cpu vendor>"; 511 if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && 512 (x86_vendor_name[vendor] != 0)) 513 name = x86_vendor_name[vendor]; 514 515 return name; 516 } 517 518 char *cpu_get_name(char *name) 519 { 520 unsigned int *name_as_ints = (unsigned int *)name; 521 struct cpuid_result regs; 522 char *ptr; 523 int i; 524 525 /* This bit adds up to 48 bytes */ 526 for (i = 0; i < 3; i++) { 527 regs = cpuid(0x80000002 + i); 528 name_as_ints[i * 4 + 0] = regs.eax; 529 name_as_ints[i * 4 + 1] = regs.ebx; 530 name_as_ints[i * 4 + 2] = regs.ecx; 531 name_as_ints[i * 4 + 3] = regs.edx; 532 } 533 name[CPU_MAX_NAME_LEN - 1] = '\0'; 534 535 /* Skip leading spaces. */ 536 ptr = name; 537 while (*ptr == ' ') 538 ptr++; 539 540 return ptr; 541 } 542 543 int x86_cpu_get_desc(struct udevice *dev, char *buf, int size) 544 { 545 if (size < CPU_MAX_NAME_LEN) 546 return -ENOSPC; 547 548 cpu_get_name(buf); 549 550 return 0; 551 } 552 553 int default_print_cpuinfo(void) 554 { 555 printf("CPU: %s, vendor %s, device %xh\n", 556 cpu_has_64bit() ? "x86_64" : "x86", 557 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); 558 559 return 0; 560 } 561 562 #define PAGETABLE_SIZE (6 * 4096) 563 564 /** 565 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode 566 * 567 * @pgtable: Pointer to a 24iKB block of memory 568 */ 569 static void build_pagetable(uint32_t *pgtable) 570 { 571 uint i; 572 573 memset(pgtable, '\0', PAGETABLE_SIZE); 574 575 /* Level 4 needs a single entry */ 576 pgtable[0] = (uint32_t)&pgtable[1024] + 7; 577 578 /* Level 3 has one 64-bit entry for each GiB of memory */ 579 for (i = 0; i < 4; i++) { 580 pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + 581 0x1000 * i + 7; 582 } 583 584 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ 585 for (i = 0; i < 2048; i++) 586 pgtable[2048 + i * 2] = 0x183 + (i << 21UL); 587 } 588 589 int cpu_jump_to_64bit(ulong setup_base, ulong target) 590 { 591 uint32_t *pgtable; 592 593 pgtable = memalign(4096, PAGETABLE_SIZE); 594 if (!pgtable) 595 return -ENOMEM; 596 597 build_pagetable(pgtable); 598 cpu_call64((ulong)pgtable, setup_base, target); 599 free(pgtable); 600 601 return -EFAULT; 602 } 603 604 void show_boot_progress(int val) 605 { 606 #if MIN_PORT80_KCLOCKS_DELAY 607 /* 608 * Scale the time counter reading to avoid using 64 bit arithmetics. 609 * Can't use get_timer() here becuase it could be not yet 610 * initialized or even implemented. 611 */ 612 if (!gd->arch.tsc_prev) { 613 gd->arch.tsc_base_kclocks = rdtsc() / 1000; 614 gd->arch.tsc_prev = 0; 615 } else { 616 uint32_t now; 617 618 do { 619 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; 620 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); 621 gd->arch.tsc_prev = now; 622 } 623 #endif 624 outb(val, POST_PORT); 625 } 626 627 #ifndef CONFIG_SYS_COREBOOT 628 int last_stage_init(void) 629 { 630 write_tables(); 631 632 return 0; 633 } 634 #endif 635 636 __weak int x86_init_cpus(void) 637 { 638 return 0; 639 } 640 641 int cpu_init_r(void) 642 { 643 return x86_init_cpus(); 644 } 645 646 static const struct cpu_ops cpu_x86_ops = { 647 .get_desc = x86_cpu_get_desc, 648 }; 649 650 static const struct udevice_id cpu_x86_ids[] = { 651 { .compatible = "cpu-x86" }, 652 { } 653 }; 654 655 U_BOOT_DRIVER(cpu_x86_drv) = { 656 .name = "cpu_x86", 657 .id = UCLASS_CPU, 658 .of_match = cpu_x86_ids, 659 .ops = &cpu_x86_ops, 660 }; 661