1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/u-boot-x86.h> 27 #include <flash.h> 28 #include <netdev.h> 29 #include <asm/msr.h> 30 #include <asm/cache.h> 31 #include <asm/arch-coreboot/tables.h> 32 #include <asm/arch-coreboot/sysinfo.h> 33 #include <asm/arch/timestamp.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; 38 39 /* 40 * Miscellaneous platform dependent initializations 41 */ 42 int cpu_init_f(void) 43 { 44 int ret = get_coreboot_info(&lib_sysinfo); 45 if (ret != 0) 46 printf("Failed to parse coreboot tables.\n"); 47 48 timestamp_init(); 49 50 return ret; 51 } 52 53 int board_early_init_f(void) 54 { 55 return 0; 56 } 57 58 int board_early_init_r(void) 59 { 60 /* CPU Speed to 100MHz */ 61 gd->cpu_clk = 100000000; 62 63 /* Crystal is 33.000MHz */ 64 gd->bus_clk = 33000000; 65 66 return 0; 67 } 68 69 void show_boot_progress(int val) 70 { 71 } 72 73 74 int last_stage_init(void) 75 { 76 return 0; 77 } 78 79 #ifndef CONFIG_SYS_NO_FLASH 80 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) 81 { 82 return 0; 83 } 84 #endif 85 86 int board_eth_init(bd_t *bis) 87 { 88 return pci_eth_init(bis); 89 } 90 91 void setup_pcat_compatibility() 92 { 93 } 94 95 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) 96 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) 97 98 int board_final_cleanup(void) 99 { 100 /* Un-cache the ROM so the kernel has one 101 * more MTRR available. 102 */ 103 disable_caches(); 104 wrmsrl(MTRRphysBase_MSR(7), 0); 105 wrmsrl(MTRRphysMask_MSR(7), 0); 106 enable_caches(); 107 108 return 0; 109 } 110