1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/u-boot-x86.h> 11 #include <flash.h> 12 #include <netdev.h> 13 #include <ns16550.h> 14 #include <asm/msr.h> 15 #include <asm/cache.h> 16 #include <asm/cpu.h> 17 #include <asm/io.h> 18 #include <asm/arch/tables.h> 19 #include <asm/arch/sysinfo.h> 20 #include <asm/arch/timestamp.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 int arch_cpu_init(void) 25 { 26 int ret = get_coreboot_info(&lib_sysinfo); 27 if (ret != 0) { 28 printf("Failed to parse coreboot tables.\n"); 29 return ret; 30 } 31 32 timestamp_init(); 33 34 return x86_cpu_init_f(); 35 } 36 37 int board_early_init_f(void) 38 { 39 return 0; 40 } 41 42 int board_early_init_r(void) 43 { 44 /* CPU Speed to 100MHz */ 45 gd->cpu_clk = 100000000; 46 47 /* Crystal is 33.000MHz */ 48 gd->bus_clk = 33000000; 49 50 return 0; 51 } 52 53 int print_cpuinfo(void) 54 { 55 return default_print_cpuinfo(); 56 } 57 58 int last_stage_init(void) 59 { 60 if (gd->flags & GD_FLG_COLD_BOOT) 61 timestamp_add_to_bootstage(); 62 63 return 0; 64 } 65 66 #ifndef CONFIG_SYS_NO_FLASH 67 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) 68 { 69 return 0; 70 } 71 #endif 72 73 int board_eth_init(bd_t *bis) 74 { 75 return pci_eth_init(bis); 76 } 77 78 #define MTRR_TYPE_WP 5 79 #define MTRRcap_MSR 0xfe 80 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) 81 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) 82 83 void board_final_cleanup(void) 84 { 85 /* Un-cache the ROM so the kernel has one 86 * more MTRR available. 87 * 88 * Coreboot should have assigned this to the 89 * top available variable MTRR. 90 */ 91 u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1; 92 u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff; 93 94 /* Make sure this MTRR is the correct Write-Protected type */ 95 if (top_type == MTRR_TYPE_WP) { 96 disable_caches(); 97 wrmsrl(MTRRphysBase_MSR(top_mtrr), 0); 98 wrmsrl(MTRRphysMask_MSR(top_mtrr), 0); 99 enable_caches(); 100 } 101 102 /* Issue SMI to Coreboot to lock down ME and registers */ 103 printf("Finalizing Coreboot\n"); 104 outb(0xcb, 0xb2); 105 } 106 107 void panic_puts(const char *str) 108 { 109 NS16550_t port = (NS16550_t)0x3f8; 110 111 NS16550_init(port, 1); 112 while (*str) 113 NS16550_putc(port, *str++); 114 } 115