1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/u-boot-x86.h> 27 #include <flash.h> 28 #include <netdev.h> 29 #include <asm/msr.h> 30 #include <asm/cache.h> 31 #include <asm/io.h> 32 #include <asm/arch-coreboot/tables.h> 33 #include <asm/arch-coreboot/sysinfo.h> 34 #include <asm/arch/timestamp.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 /* 39 * Miscellaneous platform dependent initializations 40 */ 41 int cpu_init_f(void) 42 { 43 int ret = get_coreboot_info(&lib_sysinfo); 44 if (ret != 0) 45 printf("Failed to parse coreboot tables.\n"); 46 47 timestamp_init(); 48 49 return ret; 50 } 51 52 int board_early_init_f(void) 53 { 54 return 0; 55 } 56 57 int board_early_init_r(void) 58 { 59 /* CPU Speed to 100MHz */ 60 gd->cpu_clk = 100000000; 61 62 /* Crystal is 33.000MHz */ 63 gd->bus_clk = 33000000; 64 65 return 0; 66 } 67 68 void show_boot_progress(int val) 69 { 70 #if MIN_PORT80_KCLOCKS_DELAY 71 /* 72 * Scale the time counter reading to avoid using 64 bit arithmetics. 73 * Can't use get_timer() here becuase it could be not yet 74 * initialized or even implemented. 75 */ 76 if (!gd->arch.tsc_prev) { 77 gd->arch.tsc_base_kclocks = rdtsc() / 1000; 78 gd->arch.tsc_prev = 0; 79 } else { 80 uint32_t now; 81 82 do { 83 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; 84 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); 85 gd->arch.tsc_prev = now; 86 } 87 #endif 88 outb(val, 0x80); 89 } 90 91 int last_stage_init(void) 92 { 93 return 0; 94 } 95 96 #ifndef CONFIG_SYS_NO_FLASH 97 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) 98 { 99 return 0; 100 } 101 #endif 102 103 int board_eth_init(bd_t *bis) 104 { 105 return pci_eth_init(bis); 106 } 107 108 #define MTRR_TYPE_WP 5 109 #define MTRRcap_MSR 0xfe 110 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) 111 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) 112 113 int board_final_cleanup(void) 114 { 115 /* Un-cache the ROM so the kernel has one 116 * more MTRR available. 117 * 118 * Coreboot should have assigned this to the 119 * top available variable MTRR. 120 */ 121 u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1; 122 u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff; 123 124 /* Make sure this MTRR is the correct Write-Protected type */ 125 if (top_type == MTRR_TYPE_WP) { 126 disable_caches(); 127 wrmsrl(MTRRphysBase_MSR(top_mtrr), 0); 128 wrmsrl(MTRRphysMask_MSR(top_mtrr), 0); 129 enable_caches(); 130 } 131 132 /* Issue SMI to Coreboot to lock down ME and registers */ 133 printf("Finalizing Coreboot\n"); 134 outb(0xcb, 0xb2); 135 136 return 0; 137 } 138