1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <netdev.h> 11 #include <asm/io.h> 12 #include <asm/msr.h> 13 #include <asm/mtrr.h> 14 #include <asm/arch/sysinfo.h> 15 #include <asm/arch/timestamp.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 int arch_cpu_init(void) 20 { 21 int ret = get_coreboot_info(&lib_sysinfo); 22 if (ret != 0) { 23 printf("Failed to parse coreboot tables.\n"); 24 return ret; 25 } 26 27 timestamp_init(); 28 29 return x86_cpu_init_f(); 30 } 31 32 int board_early_init_f(void) 33 { 34 return 0; 35 } 36 37 int print_cpuinfo(void) 38 { 39 return default_print_cpuinfo(); 40 } 41 42 int last_stage_init(void) 43 { 44 if (gd->flags & GD_FLG_COLD_BOOT) 45 timestamp_add_to_bootstage(); 46 47 return 0; 48 } 49 50 int board_eth_init(bd_t *bis) 51 { 52 return pci_eth_init(bis); 53 } 54 55 void board_final_cleanup(void) 56 { 57 /* 58 * Un-cache the ROM so the kernel has one 59 * more MTRR available. 60 * 61 * Coreboot should have assigned this to the 62 * top available variable MTRR. 63 */ 64 u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1; 65 u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff; 66 67 /* Make sure this MTRR is the correct Write-Protected type */ 68 if (top_type == MTRR_TYPE_WRPROT) { 69 struct mtrr_state state; 70 71 mtrr_open(&state); 72 wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0); 73 wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0); 74 mtrr_close(&state); 75 } 76 77 /* Issue SMI to Coreboot to lock down ME and registers */ 78 printf("Finalizing Coreboot\n"); 79 outb(0xcb, 0xb2); 80 } 81 82 int misc_init_r(void) 83 { 84 return 0; 85 } 86