1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/u-boot-x86.h> 27 #include <flash.h> 28 #include <netdev.h> 29 #include <ns16550.h> 30 #include <asm/msr.h> 31 #include <asm/cache.h> 32 #include <asm/io.h> 33 #include <asm/arch-coreboot/tables.h> 34 #include <asm/arch-coreboot/sysinfo.h> 35 #include <asm/arch/timestamp.h> 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Miscellaneous platform dependent initializations 41 */ 42 int cpu_init_f(void) 43 { 44 int ret = get_coreboot_info(&lib_sysinfo); 45 if (ret != 0) 46 printf("Failed to parse coreboot tables.\n"); 47 48 timestamp_init(); 49 50 return ret; 51 } 52 53 int board_early_init_f(void) 54 { 55 return 0; 56 } 57 58 int board_early_init_r(void) 59 { 60 /* CPU Speed to 100MHz */ 61 gd->cpu_clk = 100000000; 62 63 /* Crystal is 33.000MHz */ 64 gd->bus_clk = 33000000; 65 66 return 0; 67 } 68 69 void show_boot_progress(int val) 70 { 71 #if MIN_PORT80_KCLOCKS_DELAY 72 /* 73 * Scale the time counter reading to avoid using 64 bit arithmetics. 74 * Can't use get_timer() here becuase it could be not yet 75 * initialized or even implemented. 76 */ 77 if (!gd->arch.tsc_prev) { 78 gd->arch.tsc_base_kclocks = rdtsc() / 1000; 79 gd->arch.tsc_prev = 0; 80 } else { 81 uint32_t now; 82 83 do { 84 now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; 85 } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); 86 gd->arch.tsc_prev = now; 87 } 88 #endif 89 outb(val, 0x80); 90 } 91 92 int last_stage_init(void) 93 { 94 return 0; 95 } 96 97 #ifndef CONFIG_SYS_NO_FLASH 98 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) 99 { 100 return 0; 101 } 102 #endif 103 104 int board_eth_init(bd_t *bis) 105 { 106 return pci_eth_init(bis); 107 } 108 109 #define MTRR_TYPE_WP 5 110 #define MTRRcap_MSR 0xfe 111 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) 112 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) 113 114 int board_final_cleanup(void) 115 { 116 /* Un-cache the ROM so the kernel has one 117 * more MTRR available. 118 * 119 * Coreboot should have assigned this to the 120 * top available variable MTRR. 121 */ 122 u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1; 123 u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff; 124 125 /* Make sure this MTRR is the correct Write-Protected type */ 126 if (top_type == MTRR_TYPE_WP) { 127 disable_caches(); 128 wrmsrl(MTRRphysBase_MSR(top_mtrr), 0); 129 wrmsrl(MTRRphysMask_MSR(top_mtrr), 0); 130 enable_caches(); 131 } 132 133 /* Issue SMI to Coreboot to lock down ME and registers */ 134 printf("Finalizing Coreboot\n"); 135 outb(0xcb, 0xb2); 136 137 return 0; 138 } 139 140 void panic_puts(const char *str) 141 { 142 NS16550_t port = (NS16550_t)0x3f8; 143 144 NS16550_init(port, 1); 145 while (*str) 146 NS16550_putc(port, *str++); 147 } 148