1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/u-boot-x86.h> 11 #include <flash.h> 12 #include <netdev.h> 13 #include <ns16550.h> 14 #include <asm/msr.h> 15 #include <asm/cache.h> 16 #include <asm/cpu.h> 17 #include <asm/io.h> 18 #include <asm/arch/tables.h> 19 #include <asm/arch/sysinfo.h> 20 #include <asm/arch/timestamp.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 int arch_cpu_init(void) 25 { 26 int ret = get_coreboot_info(&lib_sysinfo); 27 if (ret != 0) { 28 printf("Failed to parse coreboot tables.\n"); 29 return ret; 30 } 31 32 timestamp_init(); 33 34 return x86_cpu_init_f(); 35 } 36 37 int board_early_init_f(void) 38 { 39 return 0; 40 } 41 42 int print_cpuinfo(void) 43 { 44 return default_print_cpuinfo(); 45 } 46 47 int last_stage_init(void) 48 { 49 if (gd->flags & GD_FLG_COLD_BOOT) 50 timestamp_add_to_bootstage(); 51 52 return 0; 53 } 54 55 #ifndef CONFIG_SYS_NO_FLASH 56 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) 57 { 58 return 0; 59 } 60 #endif 61 62 int board_eth_init(bd_t *bis) 63 { 64 return pci_eth_init(bis); 65 } 66 67 #define MTRR_TYPE_WP 5 68 #define MTRRcap_MSR 0xfe 69 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) 70 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) 71 72 void board_final_cleanup(void) 73 { 74 /* Un-cache the ROM so the kernel has one 75 * more MTRR available. 76 * 77 * Coreboot should have assigned this to the 78 * top available variable MTRR. 79 */ 80 u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1; 81 u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff; 82 83 /* Make sure this MTRR is the correct Write-Protected type */ 84 if (top_type == MTRR_TYPE_WP) { 85 disable_caches(); 86 wrmsrl(MTRRphysBase_MSR(top_mtrr), 0); 87 wrmsrl(MTRRphysMask_MSR(top_mtrr), 0); 88 enable_caches(); 89 } 90 91 /* Issue SMI to Coreboot to lock down ME and registers */ 92 printf("Finalizing Coreboot\n"); 93 outb(0xcb, 0xb2); 94 } 95 96 void panic_puts(const char *str) 97 { 98 NS16550_t port = (NS16550_t)0x3f8; 99 100 NS16550_init(port, 1); 101 while (*str) 102 NS16550_putc(port, *str++); 103 } 104