1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016 Google, Inc 4 * 5 * From coreboot src/soc/intel/broadwell/romstage/raminit.c 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <pci.h> 11 #include <syscon.h> 12 #include <asm/cpu.h> 13 #include <asm/io.h> 14 #include <asm/lpc_common.h> 15 #include <asm/mrccache.h> 16 #include <asm/mrc_common.h> 17 #include <asm/mtrr.h> 18 #include <asm/pci.h> 19 #include <asm/arch/iomap.h> 20 #include <asm/arch/me.h> 21 #include <asm/arch/pch.h> 22 #include <asm/arch/pei_data.h> 23 #include <asm/arch/pm.h> 24 25 ulong board_get_usable_ram_top(ulong total_size) 26 { 27 return mrc_common_board_get_usable_ram_top(total_size); 28 } 29 30 int dram_init_banksize(void) 31 { 32 mrc_common_dram_init_banksize(); 33 34 return 0; 35 } 36 37 void broadwell_fill_pei_data(struct pei_data *pei_data) 38 { 39 pei_data->pei_version = PEI_VERSION; 40 pei_data->board_type = BOARD_TYPE_ULT; 41 pei_data->pciexbar = MCFG_BASE_ADDRESS; 42 pei_data->smbusbar = SMBUS_BASE_ADDRESS; 43 pei_data->ehcibar = EARLY_EHCI_BAR; 44 pei_data->xhcibar = EARLY_XHCI_BAR; 45 pei_data->gttbar = EARLY_GTT_BAR; 46 pei_data->pmbase = ACPI_BASE_ADDRESS; 47 pei_data->gpiobase = GPIO_BASE_ADDRESS; 48 pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; 49 pei_data->temp_mmio_base = EARLY_TEMP_MMIO; 50 pei_data->tx_byte = sdram_console_tx_byte; 51 pei_data->ddr_refresh_2x = 1; 52 } 53 54 static inline void pei_data_usb2_port(struct pei_data *pei_data, int port, 55 uint16_t length, uint8_t enable, 56 uint8_t oc_pin, uint8_t location) 57 { 58 pei_data->usb2_ports[port].length = length; 59 pei_data->usb2_ports[port].enable = enable; 60 pei_data->usb2_ports[port].oc_pin = oc_pin; 61 pei_data->usb2_ports[port].location = location; 62 } 63 64 static inline void pei_data_usb3_port(struct pei_data *pei_data, int port, 65 uint8_t enable, uint8_t oc_pin, 66 uint8_t fixed_eq) 67 { 68 pei_data->usb3_ports[port].enable = enable; 69 pei_data->usb3_ports[port].oc_pin = oc_pin; 70 pei_data->usb3_ports[port].fixed_eq = fixed_eq; 71 } 72 73 void mainboard_fill_pei_data(struct pei_data *pei_data) 74 { 75 /* DQ byte map for Samus board */ 76 const u8 dq_map[2][6][2] = { 77 { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, 78 { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } }, 79 { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, 80 { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } }; 81 /* DQS CPU<>DRAM map for Samus board */ 82 const u8 dqs_map[2][8] = { 83 { 2, 0, 1, 3, 6, 4, 7, 5 }, 84 { 2, 1, 0, 3, 6, 5, 4, 7 } }; 85 86 pei_data->ec_present = 1; 87 88 /* One installed DIMM per channel */ 89 pei_data->dimm_channel0_disabled = 2; 90 pei_data->dimm_channel1_disabled = 2; 91 92 memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); 93 memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); 94 95 /* P0: HOST PORT */ 96 pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0, 97 USB_PORT_BACK_PANEL); 98 /* P1: HOST PORT */ 99 pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1, 100 USB_PORT_BACK_PANEL); 101 /* P2: RAIDEN */ 102 pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, 103 USB_PORT_BACK_PANEL); 104 /* P3: SD CARD */ 105 pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, 106 USB_PORT_INTERNAL); 107 /* P4: RAIDEN */ 108 pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, 109 USB_PORT_BACK_PANEL); 110 /* P5: WWAN (Disabled) */ 111 pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, 112 USB_PORT_SKIP); 113 /* P6: CAMERA */ 114 pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, 115 USB_PORT_INTERNAL); 116 /* P7: BT */ 117 pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, 118 USB_PORT_INTERNAL); 119 120 /* P1: HOST PORT */ 121 pei_data_usb3_port(pei_data, 0, 1, 0, 0); 122 /* P2: HOST PORT */ 123 pei_data_usb3_port(pei_data, 1, 1, 1, 0); 124 /* P3: RAIDEN */ 125 pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); 126 /* P4: RAIDEN */ 127 pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); 128 } 129 130 static unsigned long get_top_of_ram(struct udevice *dev) 131 { 132 /* 133 * Base of DPR is top of usable DRAM below 4GiB. The register has 134 * 1 MiB alignment and reports the TOP of the range, the base 135 * must be calculated from the size in MiB in bits 11:4. 136 */ 137 u32 dpr, tom; 138 139 dm_pci_read_config32(dev, DPR, &dpr); 140 tom = dpr & ~((1 << 20) - 1); 141 142 debug("dpt %08x tom %08x\n", dpr, tom); 143 /* Subtract DMA Protected Range size if enabled */ 144 if (dpr & DPR_EPM) 145 tom -= (dpr & DPR_SIZE_MASK) << 16; 146 147 return (unsigned long)tom; 148 } 149 150 /** 151 * sdram_find() - Find available memory 152 * 153 * This is a bit complicated since on x86 there are system memory holes all 154 * over the place. We create a list of available memory blocks 155 * 156 * @dev: Northbridge device 157 */ 158 static int sdram_find(struct udevice *dev) 159 { 160 struct memory_info *info = &gd->arch.meminfo; 161 ulong top_of_ram; 162 163 top_of_ram = get_top_of_ram(dev); 164 mrc_add_memory_area(info, 0, top_of_ram); 165 166 /* Add MTRRs for memory */ 167 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30); 168 169 return 0; 170 } 171 172 static int prepare_mrc_cache(struct pei_data *pei_data) 173 { 174 struct mrc_data_container *mrc_cache; 175 struct mrc_region entry; 176 int ret; 177 178 ret = mrccache_get_region(NULL, &entry); 179 if (ret) 180 return ret; 181 mrc_cache = mrccache_find_current(&entry); 182 if (!mrc_cache) 183 return -ENOENT; 184 185 pei_data->saved_data = mrc_cache->data; 186 pei_data->saved_data_size = mrc_cache->data_size; 187 debug("%s: at %p, size %x checksum %04x\n", __func__, 188 pei_data->saved_data, pei_data->saved_data_size, 189 mrc_cache->checksum); 190 191 return 0; 192 } 193 194 int dram_init(void) 195 { 196 struct pei_data _pei_data __aligned(8); 197 struct pei_data *pei_data = &_pei_data; 198 struct udevice *dev, *me_dev, *pch_dev; 199 struct chipset_power_state ps; 200 const void *spd_data; 201 int ret, size; 202 203 memset(pei_data, '\0', sizeof(struct pei_data)); 204 205 /* Print ME state before MRC */ 206 ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev); 207 if (ret) 208 return ret; 209 intel_me_status(me_dev); 210 211 /* Save ME HSIO version */ 212 ret = uclass_first_device(UCLASS_PCH, &pch_dev); 213 if (ret) 214 return ret; 215 if (!pch_dev) 216 return -ENODEV; 217 power_state_get(pch_dev, &ps); 218 219 intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum); 220 221 broadwell_fill_pei_data(pei_data); 222 mainboard_fill_pei_data(pei_data); 223 224 ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev); 225 if (ret) 226 return ret; 227 if (!dev) 228 return -ENODEV; 229 size = 256; 230 ret = mrc_locate_spd(dev, size, &spd_data); 231 if (ret) 232 return ret; 233 memcpy(pei_data->spd_data[0][0], spd_data, size); 234 memcpy(pei_data->spd_data[1][0], spd_data, size); 235 236 ret = prepare_mrc_cache(pei_data); 237 if (ret) 238 debug("prepare_mrc_cache failed: %d\n", ret); 239 240 debug("PEI version %#x\n", pei_data->pei_version); 241 ret = mrc_common_init(dev, pei_data, true); 242 if (ret) 243 return ret; 244 debug("Memory init done\n"); 245 246 ret = sdram_find(dev); 247 if (ret) 248 return ret; 249 gd->ram_size = gd->arch.meminfo.total_32bit_memory; 250 debug("RAM size %llx\n", (unsigned long long)gd->ram_size); 251 252 debug("MRC output data length %#x at %p\n", pei_data->data_to_save_size, 253 pei_data->data_to_save); 254 /* S3 resume: don't save scrambler seed or MRC data */ 255 if (pei_data->boot_mode != SLEEP_STATE_S3) { 256 /* 257 * This will be copied to SDRAM in reserve_arch(), then written 258 * to SPI flash in mrccache_save() 259 */ 260 gd->arch.mrc_output = (char *)pei_data->data_to_save; 261 gd->arch.mrc_output_len = pei_data->data_to_save_size; 262 } 263 gd->arch.pei_meminfo = pei_data->meminfo; 264 265 return 0; 266 } 267 268 /* Use this hook to save our SDRAM parameters */ 269 int misc_init_r(void) 270 { 271 int ret; 272 273 ret = mrccache_save(); 274 if (ret) 275 printf("Unable to save MRC data: %d\n", ret); 276 else 277 debug("Saved MRC cache data\n"); 278 279 return 0; 280 } 281 282 void board_debug_uart_init(void) 283 { 284 struct udevice *bus = NULL; 285 286 /* com1 / com2 decode range */ 287 pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16); 288 289 pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN, 290 PCI_SIZE_16); 291 } 292 293 static const struct udevice_id broadwell_syscon_ids[] = { 294 { .compatible = "intel,me", .data = X86_SYSCON_ME }, 295 { } 296 }; 297 298 U_BOOT_DRIVER(syscon_intel_me) = { 299 .name = "intel_me_syscon", 300 .id = UCLASS_SYSCON, 301 .of_match = broadwell_syscon_ids, 302 }; 303