1 /* 2 * Copyright (c) 2016 Google, Inc 3 * 4 * From coreboot src/soc/intel/broadwell/romstage/raminit.c 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <pci.h> 12 #include <syscon.h> 13 #include <asm/cpu.h> 14 #include <asm/io.h> 15 #include <asm/lpc_common.h> 16 #include <asm/mrccache.h> 17 #include <asm/mrc_common.h> 18 #include <asm/mtrr.h> 19 #include <asm/pci.h> 20 #include <asm/arch/iomap.h> 21 #include <asm/arch/me.h> 22 #include <asm/arch/pch.h> 23 #include <asm/arch/pei_data.h> 24 #include <asm/arch/pm.h> 25 26 ulong board_get_usable_ram_top(ulong total_size) 27 { 28 return mrc_common_board_get_usable_ram_top(total_size); 29 } 30 31 void dram_init_banksize(void) 32 { 33 mrc_common_dram_init_banksize(); 34 } 35 36 void broadwell_fill_pei_data(struct pei_data *pei_data) 37 { 38 pei_data->pei_version = PEI_VERSION; 39 pei_data->board_type = BOARD_TYPE_ULT; 40 pei_data->pciexbar = MCFG_BASE_ADDRESS; 41 pei_data->smbusbar = SMBUS_BASE_ADDRESS; 42 pei_data->ehcibar = EARLY_EHCI_BAR; 43 pei_data->xhcibar = EARLY_XHCI_BAR; 44 pei_data->gttbar = EARLY_GTT_BAR; 45 pei_data->pmbase = ACPI_BASE_ADDRESS; 46 pei_data->gpiobase = GPIO_BASE_ADDRESS; 47 pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; 48 pei_data->temp_mmio_base = EARLY_TEMP_MMIO; 49 pei_data->tx_byte = sdram_console_tx_byte; 50 pei_data->ddr_refresh_2x = 1; 51 } 52 53 static inline void pei_data_usb2_port(struct pei_data *pei_data, int port, 54 uint16_t length, uint8_t enable, 55 uint8_t oc_pin, uint8_t location) 56 { 57 pei_data->usb2_ports[port].length = length; 58 pei_data->usb2_ports[port].enable = enable; 59 pei_data->usb2_ports[port].oc_pin = oc_pin; 60 pei_data->usb2_ports[port].location = location; 61 } 62 63 static inline void pei_data_usb3_port(struct pei_data *pei_data, int port, 64 uint8_t enable, uint8_t oc_pin, 65 uint8_t fixed_eq) 66 { 67 pei_data->usb3_ports[port].enable = enable; 68 pei_data->usb3_ports[port].oc_pin = oc_pin; 69 pei_data->usb3_ports[port].fixed_eq = fixed_eq; 70 } 71 72 void mainboard_fill_pei_data(struct pei_data *pei_data) 73 { 74 /* DQ byte map for Samus board */ 75 const u8 dq_map[2][6][2] = { 76 { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, 77 { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } }, 78 { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, 79 { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } }; 80 /* DQS CPU<>DRAM map for Samus board */ 81 const u8 dqs_map[2][8] = { 82 { 2, 0, 1, 3, 6, 4, 7, 5 }, 83 { 2, 1, 0, 3, 6, 5, 4, 7 } }; 84 85 pei_data->ec_present = 1; 86 87 /* One installed DIMM per channel */ 88 pei_data->dimm_channel0_disabled = 2; 89 pei_data->dimm_channel1_disabled = 2; 90 91 memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); 92 memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); 93 94 /* P0: HOST PORT */ 95 pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0, 96 USB_PORT_BACK_PANEL); 97 /* P1: HOST PORT */ 98 pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1, 99 USB_PORT_BACK_PANEL); 100 /* P2: RAIDEN */ 101 pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, 102 USB_PORT_BACK_PANEL); 103 /* P3: SD CARD */ 104 pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, 105 USB_PORT_INTERNAL); 106 /* P4: RAIDEN */ 107 pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, 108 USB_PORT_BACK_PANEL); 109 /* P5: WWAN (Disabled) */ 110 pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, 111 USB_PORT_SKIP); 112 /* P6: CAMERA */ 113 pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, 114 USB_PORT_INTERNAL); 115 /* P7: BT */ 116 pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, 117 USB_PORT_INTERNAL); 118 119 /* P1: HOST PORT */ 120 pei_data_usb3_port(pei_data, 0, 1, 0, 0); 121 /* P2: HOST PORT */ 122 pei_data_usb3_port(pei_data, 1, 1, 1, 0); 123 /* P3: RAIDEN */ 124 pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); 125 /* P4: RAIDEN */ 126 pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); 127 } 128 129 static unsigned long get_top_of_ram(struct udevice *dev) 130 { 131 /* 132 * Base of DPR is top of usable DRAM below 4GiB. The register has 133 * 1 MiB alignment and reports the TOP of the range, the base 134 * must be calculated from the size in MiB in bits 11:4. 135 */ 136 u32 dpr, tom; 137 138 dm_pci_read_config32(dev, DPR, &dpr); 139 tom = dpr & ~((1 << 20) - 1); 140 141 debug("dpt %08x tom %08x\n", dpr, tom); 142 /* Subtract DMA Protected Range size if enabled */ 143 if (dpr & DPR_EPM) 144 tom -= (dpr & DPR_SIZE_MASK) << 16; 145 146 return (unsigned long)tom; 147 } 148 149 /** 150 * sdram_find() - Find available memory 151 * 152 * This is a bit complicated since on x86 there are system memory holes all 153 * over the place. We create a list of available memory blocks 154 * 155 * @dev: Northbridge device 156 */ 157 static int sdram_find(struct udevice *dev) 158 { 159 struct memory_info *info = &gd->arch.meminfo; 160 ulong top_of_ram; 161 162 top_of_ram = get_top_of_ram(dev); 163 mrc_add_memory_area(info, 0, top_of_ram); 164 165 /* Add MTRRs for memory */ 166 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30); 167 168 return 0; 169 } 170 171 static int prepare_mrc_cache(struct pei_data *pei_data) 172 { 173 struct mrc_data_container *mrc_cache; 174 struct mrc_region entry; 175 int ret; 176 177 ret = mrccache_get_region(NULL, &entry); 178 if (ret) 179 return ret; 180 mrc_cache = mrccache_find_current(&entry); 181 if (!mrc_cache) 182 return -ENOENT; 183 184 pei_data->saved_data = mrc_cache->data; 185 pei_data->saved_data_size = mrc_cache->data_size; 186 debug("%s: at %p, size %x checksum %04x\n", __func__, 187 pei_data->saved_data, pei_data->saved_data_size, 188 mrc_cache->checksum); 189 190 return 0; 191 } 192 193 int dram_init(void) 194 { 195 struct pei_data _pei_data __aligned(8); 196 struct pei_data *pei_data = &_pei_data; 197 struct udevice *dev, *me_dev, *pch_dev; 198 struct chipset_power_state ps; 199 const void *spd_data; 200 int ret, size; 201 202 memset(pei_data, '\0', sizeof(struct pei_data)); 203 204 /* Print ME state before MRC */ 205 ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev); 206 if (ret) 207 return ret; 208 intel_me_status(me_dev); 209 210 /* Save ME HSIO version */ 211 ret = uclass_first_device(UCLASS_PCH, &pch_dev); 212 if (ret) 213 return ret; 214 if (!pch_dev) 215 return -ENODEV; 216 power_state_get(pch_dev, &ps); 217 218 intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum); 219 220 broadwell_fill_pei_data(pei_data); 221 mainboard_fill_pei_data(pei_data); 222 223 ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev); 224 if (ret) 225 return ret; 226 if (!dev) 227 return -ENODEV; 228 size = 256; 229 ret = mrc_locate_spd(dev, size, &spd_data); 230 if (ret) 231 return ret; 232 memcpy(pei_data->spd_data[0][0], spd_data, size); 233 memcpy(pei_data->spd_data[1][0], spd_data, size); 234 235 ret = prepare_mrc_cache(pei_data); 236 if (ret) 237 debug("prepare_mrc_cache failed: %d\n", ret); 238 239 debug("PEI version %#x\n", pei_data->pei_version); 240 ret = mrc_common_init(dev, pei_data, true); 241 if (ret) 242 return ret; 243 debug("Memory init done\n"); 244 245 ret = sdram_find(dev); 246 if (ret) 247 return ret; 248 gd->ram_size = gd->arch.meminfo.total_32bit_memory; 249 debug("RAM size %llx\n", (unsigned long long)gd->ram_size); 250 251 debug("MRC output data length %#x at %p\n", pei_data->data_to_save_size, 252 pei_data->data_to_save); 253 /* S3 resume: don't save scrambler seed or MRC data */ 254 if (pei_data->boot_mode != SLEEP_STATE_S3) { 255 /* 256 * This will be copied to SDRAM in reserve_arch(), then written 257 * to SPI flash in mrccache_save() 258 */ 259 gd->arch.mrc_output = (char *)pei_data->data_to_save; 260 gd->arch.mrc_output_len = pei_data->data_to_save_size; 261 } 262 gd->arch.pei_meminfo = pei_data->meminfo; 263 264 return 0; 265 } 266 267 /* Use this hook to save our SDRAM parameters */ 268 int misc_init_r(void) 269 { 270 int ret; 271 272 ret = mrccache_save(); 273 if (ret) 274 printf("Unable to save MRC data: %d\n", ret); 275 else 276 debug("Saved MRC cache data\n"); 277 278 return 0; 279 } 280 281 void board_debug_uart_init(void) 282 { 283 struct udevice *bus = NULL; 284 285 /* com1 / com2 decode range */ 286 pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16); 287 288 pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN, 289 PCI_SIZE_16); 290 } 291 292 static const struct udevice_id broadwell_syscon_ids[] = { 293 { .compatible = "intel,me", .data = X86_SYSCON_ME }, 294 { .compatible = "intel,gma", .data = X86_SYSCON_GMA }, 295 { } 296 }; 297 298 U_BOOT_DRIVER(syscon_intel_me) = { 299 .name = "intel_me_syscon", 300 .id = UCLASS_SYSCON, 301 .of_match = broadwell_syscon_ids, 302 }; 303