1 /* 2 * Copyright (c) 2016 Google, Inc 3 * 4 * From coreboot src/soc/intel/broadwell/romstage/raminit.c 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <pci.h> 12 #include <syscon.h> 13 #include <asm/cpu.h> 14 #include <asm/io.h> 15 #include <asm/lpc_common.h> 16 #include <asm/mrccache.h> 17 #include <asm/mrc_common.h> 18 #include <asm/mtrr.h> 19 #include <asm/pci.h> 20 #include <asm/arch/iomap.h> 21 #include <asm/arch/me.h> 22 #include <asm/arch/pch.h> 23 #include <asm/arch/pei_data.h> 24 #include <asm/arch/pm.h> 25 26 ulong board_get_usable_ram_top(ulong total_size) 27 { 28 return mrc_common_board_get_usable_ram_top(total_size); 29 } 30 31 int dram_init_banksize(void) 32 { 33 mrc_common_dram_init_banksize(); 34 35 return 0; 36 } 37 38 void broadwell_fill_pei_data(struct pei_data *pei_data) 39 { 40 pei_data->pei_version = PEI_VERSION; 41 pei_data->board_type = BOARD_TYPE_ULT; 42 pei_data->pciexbar = MCFG_BASE_ADDRESS; 43 pei_data->smbusbar = SMBUS_BASE_ADDRESS; 44 pei_data->ehcibar = EARLY_EHCI_BAR; 45 pei_data->xhcibar = EARLY_XHCI_BAR; 46 pei_data->gttbar = EARLY_GTT_BAR; 47 pei_data->pmbase = ACPI_BASE_ADDRESS; 48 pei_data->gpiobase = GPIO_BASE_ADDRESS; 49 pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; 50 pei_data->temp_mmio_base = EARLY_TEMP_MMIO; 51 pei_data->tx_byte = sdram_console_tx_byte; 52 pei_data->ddr_refresh_2x = 1; 53 } 54 55 static inline void pei_data_usb2_port(struct pei_data *pei_data, int port, 56 uint16_t length, uint8_t enable, 57 uint8_t oc_pin, uint8_t location) 58 { 59 pei_data->usb2_ports[port].length = length; 60 pei_data->usb2_ports[port].enable = enable; 61 pei_data->usb2_ports[port].oc_pin = oc_pin; 62 pei_data->usb2_ports[port].location = location; 63 } 64 65 static inline void pei_data_usb3_port(struct pei_data *pei_data, int port, 66 uint8_t enable, uint8_t oc_pin, 67 uint8_t fixed_eq) 68 { 69 pei_data->usb3_ports[port].enable = enable; 70 pei_data->usb3_ports[port].oc_pin = oc_pin; 71 pei_data->usb3_ports[port].fixed_eq = fixed_eq; 72 } 73 74 void mainboard_fill_pei_data(struct pei_data *pei_data) 75 { 76 /* DQ byte map for Samus board */ 77 const u8 dq_map[2][6][2] = { 78 { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, 79 { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } }, 80 { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, 81 { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } }; 82 /* DQS CPU<>DRAM map for Samus board */ 83 const u8 dqs_map[2][8] = { 84 { 2, 0, 1, 3, 6, 4, 7, 5 }, 85 { 2, 1, 0, 3, 6, 5, 4, 7 } }; 86 87 pei_data->ec_present = 1; 88 89 /* One installed DIMM per channel */ 90 pei_data->dimm_channel0_disabled = 2; 91 pei_data->dimm_channel1_disabled = 2; 92 93 memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); 94 memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); 95 96 /* P0: HOST PORT */ 97 pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0, 98 USB_PORT_BACK_PANEL); 99 /* P1: HOST PORT */ 100 pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1, 101 USB_PORT_BACK_PANEL); 102 /* P2: RAIDEN */ 103 pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, 104 USB_PORT_BACK_PANEL); 105 /* P3: SD CARD */ 106 pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, 107 USB_PORT_INTERNAL); 108 /* P4: RAIDEN */ 109 pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, 110 USB_PORT_BACK_PANEL); 111 /* P5: WWAN (Disabled) */ 112 pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, 113 USB_PORT_SKIP); 114 /* P6: CAMERA */ 115 pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, 116 USB_PORT_INTERNAL); 117 /* P7: BT */ 118 pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, 119 USB_PORT_INTERNAL); 120 121 /* P1: HOST PORT */ 122 pei_data_usb3_port(pei_data, 0, 1, 0, 0); 123 /* P2: HOST PORT */ 124 pei_data_usb3_port(pei_data, 1, 1, 1, 0); 125 /* P3: RAIDEN */ 126 pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); 127 /* P4: RAIDEN */ 128 pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); 129 } 130 131 static unsigned long get_top_of_ram(struct udevice *dev) 132 { 133 /* 134 * Base of DPR is top of usable DRAM below 4GiB. The register has 135 * 1 MiB alignment and reports the TOP of the range, the base 136 * must be calculated from the size in MiB in bits 11:4. 137 */ 138 u32 dpr, tom; 139 140 dm_pci_read_config32(dev, DPR, &dpr); 141 tom = dpr & ~((1 << 20) - 1); 142 143 debug("dpt %08x tom %08x\n", dpr, tom); 144 /* Subtract DMA Protected Range size if enabled */ 145 if (dpr & DPR_EPM) 146 tom -= (dpr & DPR_SIZE_MASK) << 16; 147 148 return (unsigned long)tom; 149 } 150 151 /** 152 * sdram_find() - Find available memory 153 * 154 * This is a bit complicated since on x86 there are system memory holes all 155 * over the place. We create a list of available memory blocks 156 * 157 * @dev: Northbridge device 158 */ 159 static int sdram_find(struct udevice *dev) 160 { 161 struct memory_info *info = &gd->arch.meminfo; 162 ulong top_of_ram; 163 164 top_of_ram = get_top_of_ram(dev); 165 mrc_add_memory_area(info, 0, top_of_ram); 166 167 /* Add MTRRs for memory */ 168 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30); 169 170 return 0; 171 } 172 173 static int prepare_mrc_cache(struct pei_data *pei_data) 174 { 175 struct mrc_data_container *mrc_cache; 176 struct mrc_region entry; 177 int ret; 178 179 ret = mrccache_get_region(NULL, &entry); 180 if (ret) 181 return ret; 182 mrc_cache = mrccache_find_current(&entry); 183 if (!mrc_cache) 184 return -ENOENT; 185 186 pei_data->saved_data = mrc_cache->data; 187 pei_data->saved_data_size = mrc_cache->data_size; 188 debug("%s: at %p, size %x checksum %04x\n", __func__, 189 pei_data->saved_data, pei_data->saved_data_size, 190 mrc_cache->checksum); 191 192 return 0; 193 } 194 195 int dram_init(void) 196 { 197 struct pei_data _pei_data __aligned(8); 198 struct pei_data *pei_data = &_pei_data; 199 struct udevice *dev, *me_dev, *pch_dev; 200 struct chipset_power_state ps; 201 const void *spd_data; 202 int ret, size; 203 204 memset(pei_data, '\0', sizeof(struct pei_data)); 205 206 /* Print ME state before MRC */ 207 ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev); 208 if (ret) 209 return ret; 210 intel_me_status(me_dev); 211 212 /* Save ME HSIO version */ 213 ret = uclass_first_device(UCLASS_PCH, &pch_dev); 214 if (ret) 215 return ret; 216 if (!pch_dev) 217 return -ENODEV; 218 power_state_get(pch_dev, &ps); 219 220 intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum); 221 222 broadwell_fill_pei_data(pei_data); 223 mainboard_fill_pei_data(pei_data); 224 225 ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev); 226 if (ret) 227 return ret; 228 if (!dev) 229 return -ENODEV; 230 size = 256; 231 ret = mrc_locate_spd(dev, size, &spd_data); 232 if (ret) 233 return ret; 234 memcpy(pei_data->spd_data[0][0], spd_data, size); 235 memcpy(pei_data->spd_data[1][0], spd_data, size); 236 237 ret = prepare_mrc_cache(pei_data); 238 if (ret) 239 debug("prepare_mrc_cache failed: %d\n", ret); 240 241 debug("PEI version %#x\n", pei_data->pei_version); 242 ret = mrc_common_init(dev, pei_data, true); 243 if (ret) 244 return ret; 245 debug("Memory init done\n"); 246 247 ret = sdram_find(dev); 248 if (ret) 249 return ret; 250 gd->ram_size = gd->arch.meminfo.total_32bit_memory; 251 debug("RAM size %llx\n", (unsigned long long)gd->ram_size); 252 253 debug("MRC output data length %#x at %p\n", pei_data->data_to_save_size, 254 pei_data->data_to_save); 255 /* S3 resume: don't save scrambler seed or MRC data */ 256 if (pei_data->boot_mode != SLEEP_STATE_S3) { 257 /* 258 * This will be copied to SDRAM in reserve_arch(), then written 259 * to SPI flash in mrccache_save() 260 */ 261 gd->arch.mrc_output = (char *)pei_data->data_to_save; 262 gd->arch.mrc_output_len = pei_data->data_to_save_size; 263 } 264 gd->arch.pei_meminfo = pei_data->meminfo; 265 266 return 0; 267 } 268 269 /* Use this hook to save our SDRAM parameters */ 270 int misc_init_r(void) 271 { 272 int ret; 273 274 ret = mrccache_save(); 275 if (ret) 276 printf("Unable to save MRC data: %d\n", ret); 277 else 278 debug("Saved MRC cache data\n"); 279 280 return 0; 281 } 282 283 void board_debug_uart_init(void) 284 { 285 struct udevice *bus = NULL; 286 287 /* com1 / com2 decode range */ 288 pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16); 289 290 pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN, 291 PCI_SIZE_16); 292 } 293 294 static const struct udevice_id broadwell_syscon_ids[] = { 295 { .compatible = "intel,me", .data = X86_SYSCON_ME }, 296 { } 297 }; 298 299 U_BOOT_DRIVER(syscon_intel_me) = { 300 .name = "intel_me_syscon", 301 .id = UCLASS_SYSCON, 302 .of_match = broadwell_syscon_ids, 303 }; 304