1*b24f5c4fSSimon Glass /* 2*b24f5c4fSSimon Glass * Copyright (C) 2016 Google, Inc 3*b24f5c4fSSimon Glass * 4*b24f5c4fSSimon Glass * SPDX-License-Identifier: GPL-2.0+ 5*b24f5c4fSSimon Glass */ 6*b24f5c4fSSimon Glass 7*b24f5c4fSSimon Glass #include <common.h> 8*b24f5c4fSSimon Glass #include <dm.h> 9*b24f5c4fSSimon Glass #include <errno.h> 10*b24f5c4fSSimon Glass #include <fdtdec.h> 11*b24f5c4fSSimon Glass #include <pch.h> 12*b24f5c4fSSimon Glass #include <pci.h> 13*b24f5c4fSSimon Glass #include <asm/cpu.h> 14*b24f5c4fSSimon Glass #include <asm/gpio.h> 15*b24f5c4fSSimon Glass #include <asm/io.h> 16*b24f5c4fSSimon Glass #include <asm/pci.h> 17*b24f5c4fSSimon Glass #include <asm/arch/gpio.h> 18*b24f5c4fSSimon Glass #include <dt-bindings/gpio/x86-gpio.h> 19*b24f5c4fSSimon Glass #include <dm/pinctrl.h> 20*b24f5c4fSSimon Glass 21*b24f5c4fSSimon Glass DECLARE_GLOBAL_DATA_PTR; 22*b24f5c4fSSimon Glass 23*b24f5c4fSSimon Glass enum { 24*b24f5c4fSSimon Glass MAX_GPIOS = 95, 25*b24f5c4fSSimon Glass }; 26*b24f5c4fSSimon Glass 27*b24f5c4fSSimon Glass #define PIRQ_SHIFT 16 28*b24f5c4fSSimon Glass #define CONF_MASK 0xffff 29*b24f5c4fSSimon Glass 30*b24f5c4fSSimon Glass struct pin_info { 31*b24f5c4fSSimon Glass int node; 32*b24f5c4fSSimon Glass int phandle; 33*b24f5c4fSSimon Glass bool mode_gpio; 34*b24f5c4fSSimon Glass bool dir_input; 35*b24f5c4fSSimon Glass bool invert; 36*b24f5c4fSSimon Glass bool trigger_level; 37*b24f5c4fSSimon Glass bool output_high; 38*b24f5c4fSSimon Glass bool sense_disable; 39*b24f5c4fSSimon Glass bool owner_gpio; 40*b24f5c4fSSimon Glass bool route_smi; 41*b24f5c4fSSimon Glass bool irq_enable; 42*b24f5c4fSSimon Glass bool reset_rsmrst; 43*b24f5c4fSSimon Glass bool pirq_apic_route; 44*b24f5c4fSSimon Glass }; 45*b24f5c4fSSimon Glass 46*b24f5c4fSSimon Glass static int broadwell_pinctrl_read_configs(struct udevice *dev, 47*b24f5c4fSSimon Glass struct pin_info *conf, int max_pins) 48*b24f5c4fSSimon Glass { 49*b24f5c4fSSimon Glass const void *blob = gd->fdt_blob; 50*b24f5c4fSSimon Glass int count = 0; 51*b24f5c4fSSimon Glass int node; 52*b24f5c4fSSimon Glass 53*b24f5c4fSSimon Glass debug("%s: starting\n", __func__); 54*b24f5c4fSSimon Glass for (node = fdt_first_subnode(blob, dev->of_offset); 55*b24f5c4fSSimon Glass node > 0; 56*b24f5c4fSSimon Glass node = fdt_next_subnode(blob, node)) { 57*b24f5c4fSSimon Glass int phandle = fdt_get_phandle(blob, node); 58*b24f5c4fSSimon Glass 59*b24f5c4fSSimon Glass if (!phandle) 60*b24f5c4fSSimon Glass continue; 61*b24f5c4fSSimon Glass if (count == max_pins) 62*b24f5c4fSSimon Glass return -ENOSPC; 63*b24f5c4fSSimon Glass 64*b24f5c4fSSimon Glass /* We've found a new configuration */ 65*b24f5c4fSSimon Glass memset(conf, '\0', sizeof(*conf)); 66*b24f5c4fSSimon Glass conf->node = node; 67*b24f5c4fSSimon Glass conf->phandle = phandle; 68*b24f5c4fSSimon Glass conf->mode_gpio = fdtdec_get_bool(blob, node, "mode-gpio"); 69*b24f5c4fSSimon Glass if (fdtdec_get_int(blob, node, "direction", -1) == PIN_INPUT) 70*b24f5c4fSSimon Glass conf->dir_input = true; 71*b24f5c4fSSimon Glass conf->invert = fdtdec_get_bool(blob, node, "invert"); 72*b24f5c4fSSimon Glass if (fdtdec_get_int(blob, node, "trigger", -1) == TRIGGER_LEVEL) 73*b24f5c4fSSimon Glass conf->trigger_level = true; 74*b24f5c4fSSimon Glass if (fdtdec_get_int(blob, node, "output-value", -1) == 1) 75*b24f5c4fSSimon Glass conf->output_high = true; 76*b24f5c4fSSimon Glass conf->sense_disable = fdtdec_get_bool(blob, node, 77*b24f5c4fSSimon Glass "sense-disable"); 78*b24f5c4fSSimon Glass if (fdtdec_get_int(blob, node, "owner", -1) == OWNER_GPIO) 79*b24f5c4fSSimon Glass conf->owner_gpio = true; 80*b24f5c4fSSimon Glass if (fdtdec_get_int(blob, node, "route", -1) == ROUTE_SMI) 81*b24f5c4fSSimon Glass conf->route_smi = true; 82*b24f5c4fSSimon Glass conf->irq_enable = fdtdec_get_bool(blob, node, "irq-enable"); 83*b24f5c4fSSimon Glass conf->reset_rsmrst = fdtdec_get_bool(blob, node, 84*b24f5c4fSSimon Glass "reset-rsmrst"); 85*b24f5c4fSSimon Glass if (fdtdec_get_int(blob, node, "pirq-apic", -1) == 86*b24f5c4fSSimon Glass PIRQ_APIC_ROUTE) 87*b24f5c4fSSimon Glass conf->pirq_apic_route = true; 88*b24f5c4fSSimon Glass debug("config: phandle=%d\n", phandle); 89*b24f5c4fSSimon Glass count++; 90*b24f5c4fSSimon Glass conf++; 91*b24f5c4fSSimon Glass } 92*b24f5c4fSSimon Glass debug("%s: Found %d configurations\n", __func__, count); 93*b24f5c4fSSimon Glass 94*b24f5c4fSSimon Glass return count; 95*b24f5c4fSSimon Glass } 96*b24f5c4fSSimon Glass 97*b24f5c4fSSimon Glass static int broadwell_pinctrl_lookup_phandle(struct pin_info *conf, 98*b24f5c4fSSimon Glass int conf_count, int phandle) 99*b24f5c4fSSimon Glass { 100*b24f5c4fSSimon Glass int i; 101*b24f5c4fSSimon Glass 102*b24f5c4fSSimon Glass for (i = 0; i < conf_count; i++) { 103*b24f5c4fSSimon Glass if (conf[i].phandle == phandle) 104*b24f5c4fSSimon Glass return i; 105*b24f5c4fSSimon Glass } 106*b24f5c4fSSimon Glass 107*b24f5c4fSSimon Glass return -ENOENT; 108*b24f5c4fSSimon Glass } 109*b24f5c4fSSimon Glass 110*b24f5c4fSSimon Glass static int broadwell_pinctrl_read_pins(struct udevice *dev, 111*b24f5c4fSSimon Glass struct pin_info *conf, int conf_count, int gpio_conf[], 112*b24f5c4fSSimon Glass int num_gpios) 113*b24f5c4fSSimon Glass { 114*b24f5c4fSSimon Glass const void *blob = gd->fdt_blob; 115*b24f5c4fSSimon Glass int count = 0; 116*b24f5c4fSSimon Glass int node; 117*b24f5c4fSSimon Glass 118*b24f5c4fSSimon Glass for (node = fdt_first_subnode(blob, dev->of_offset); 119*b24f5c4fSSimon Glass node > 0; 120*b24f5c4fSSimon Glass node = fdt_next_subnode(blob, node)) { 121*b24f5c4fSSimon Glass int len, i; 122*b24f5c4fSSimon Glass const u32 *prop = fdt_getprop(blob, node, "config", &len); 123*b24f5c4fSSimon Glass 124*b24f5c4fSSimon Glass if (!prop) 125*b24f5c4fSSimon Glass continue; 126*b24f5c4fSSimon Glass 127*b24f5c4fSSimon Glass /* There are three cells per pin */ 128*b24f5c4fSSimon Glass count = len / (sizeof(u32) * 3); 129*b24f5c4fSSimon Glass debug("Found %d GPIOs to configure\n", count); 130*b24f5c4fSSimon Glass for (i = 0; i < count; i++) { 131*b24f5c4fSSimon Glass uint gpio = fdt32_to_cpu(prop[i * 3]); 132*b24f5c4fSSimon Glass uint phandle = fdt32_to_cpu(prop[i * 3 + 1]); 133*b24f5c4fSSimon Glass int val; 134*b24f5c4fSSimon Glass 135*b24f5c4fSSimon Glass if (gpio >= num_gpios) { 136*b24f5c4fSSimon Glass debug("%s: GPIO %d out of range\n", __func__, 137*b24f5c4fSSimon Glass gpio); 138*b24f5c4fSSimon Glass return -EDOM; 139*b24f5c4fSSimon Glass } 140*b24f5c4fSSimon Glass val = broadwell_pinctrl_lookup_phandle(conf, conf_count, 141*b24f5c4fSSimon Glass phandle); 142*b24f5c4fSSimon Glass if (val < 0) { 143*b24f5c4fSSimon Glass debug("%s: Cannot find phandle %d\n", __func__, 144*b24f5c4fSSimon Glass phandle); 145*b24f5c4fSSimon Glass return -EINVAL; 146*b24f5c4fSSimon Glass } 147*b24f5c4fSSimon Glass gpio_conf[gpio] = val | 148*b24f5c4fSSimon Glass fdt32_to_cpu(prop[i * 3 + 2]) << PIRQ_SHIFT; 149*b24f5c4fSSimon Glass } 150*b24f5c4fSSimon Glass } 151*b24f5c4fSSimon Glass 152*b24f5c4fSSimon Glass return 0; 153*b24f5c4fSSimon Glass } 154*b24f5c4fSSimon Glass 155*b24f5c4fSSimon Glass static void broadwell_pinctrl_commit(struct pch_lp_gpio_regs *regs, 156*b24f5c4fSSimon Glass struct pin_info *pin_info, 157*b24f5c4fSSimon Glass int gpio_conf[], int count) 158*b24f5c4fSSimon Glass { 159*b24f5c4fSSimon Glass u32 owner_gpio[GPIO_BANKS] = {0}; 160*b24f5c4fSSimon Glass u32 route_smi[GPIO_BANKS] = {0}; 161*b24f5c4fSSimon Glass u32 irq_enable[GPIO_BANKS] = {0}; 162*b24f5c4fSSimon Glass u32 reset_rsmrst[GPIO_BANKS] = {0}; 163*b24f5c4fSSimon Glass u32 pirq2apic = 0; 164*b24f5c4fSSimon Glass int set, bit, gpio = 0; 165*b24f5c4fSSimon Glass 166*b24f5c4fSSimon Glass for (gpio = 0; gpio < MAX_GPIOS; gpio++) { 167*b24f5c4fSSimon Glass int confnum = gpio_conf[gpio] & CONF_MASK; 168*b24f5c4fSSimon Glass struct pin_info *pin = &pin_info[confnum]; 169*b24f5c4fSSimon Glass u32 val; 170*b24f5c4fSSimon Glass 171*b24f5c4fSSimon Glass val = pin->mode_gpio << CONFA_MODE_SHIFT | 172*b24f5c4fSSimon Glass pin->dir_input << CONFA_DIR_SHIFT | 173*b24f5c4fSSimon Glass pin->invert << CONFA_INVERT_SHIFT | 174*b24f5c4fSSimon Glass pin->trigger_level << CONFA_TRIGGER_SHIFT | 175*b24f5c4fSSimon Glass pin->output_high << CONFA_OUTPUT_SHIFT; 176*b24f5c4fSSimon Glass outl(val, ®s->config[gpio].conf_a); 177*b24f5c4fSSimon Glass outl(pin->sense_disable << CONFB_SENSE_SHIFT, 178*b24f5c4fSSimon Glass ®s->config[gpio].conf_b); 179*b24f5c4fSSimon Glass 180*b24f5c4fSSimon Glass /* Determine set and bit based on GPIO number */ 181*b24f5c4fSSimon Glass set = gpio / GPIO_PER_BANK; 182*b24f5c4fSSimon Glass bit = gpio % GPIO_PER_BANK; 183*b24f5c4fSSimon Glass 184*b24f5c4fSSimon Glass /* Apply settings to set specific bits */ 185*b24f5c4fSSimon Glass owner_gpio[set] |= pin->owner_gpio << bit; 186*b24f5c4fSSimon Glass route_smi[set] |= pin->route_smi << bit; 187*b24f5c4fSSimon Glass irq_enable[set] |= pin->irq_enable << bit; 188*b24f5c4fSSimon Glass reset_rsmrst[set] |= pin->reset_rsmrst << bit; 189*b24f5c4fSSimon Glass 190*b24f5c4fSSimon Glass /* PIRQ to IO-APIC map */ 191*b24f5c4fSSimon Glass if (pin->pirq_apic_route) 192*b24f5c4fSSimon Glass pirq2apic |= gpio_conf[gpio] >> PIRQ_SHIFT; 193*b24f5c4fSSimon Glass debug("gpio %d: conf %d, mode_gpio %d, dir_input %d, output_high %d\n", 194*b24f5c4fSSimon Glass gpio, confnum, pin->mode_gpio, pin->dir_input, 195*b24f5c4fSSimon Glass pin->output_high); 196*b24f5c4fSSimon Glass } 197*b24f5c4fSSimon Glass 198*b24f5c4fSSimon Glass for (set = 0; set < GPIO_BANKS; set++) { 199*b24f5c4fSSimon Glass outl(owner_gpio[set], ®s->own[set]); 200*b24f5c4fSSimon Glass outl(route_smi[set], ®s->gpi_route[set]); 201*b24f5c4fSSimon Glass outl(irq_enable[set], ®s->gpi_ie[set]); 202*b24f5c4fSSimon Glass outl(reset_rsmrst[set], ®s->rst_sel[set]); 203*b24f5c4fSSimon Glass } 204*b24f5c4fSSimon Glass 205*b24f5c4fSSimon Glass outl(pirq2apic, ®s->pirq_to_ioxapic); 206*b24f5c4fSSimon Glass } 207*b24f5c4fSSimon Glass 208*b24f5c4fSSimon Glass static int broadwell_pinctrl_probe(struct udevice *dev) 209*b24f5c4fSSimon Glass { 210*b24f5c4fSSimon Glass struct pch_lp_gpio_regs *regs; 211*b24f5c4fSSimon Glass struct pin_info conf[12]; 212*b24f5c4fSSimon Glass int gpio_conf[MAX_GPIOS]; 213*b24f5c4fSSimon Glass struct udevice *pch; 214*b24f5c4fSSimon Glass int conf_count; 215*b24f5c4fSSimon Glass u32 gpiobase; 216*b24f5c4fSSimon Glass int ret; 217*b24f5c4fSSimon Glass 218*b24f5c4fSSimon Glass ret = uclass_first_device(UCLASS_PCH, &pch); 219*b24f5c4fSSimon Glass if (ret) 220*b24f5c4fSSimon Glass return ret; 221*b24f5c4fSSimon Glass if (!pch) 222*b24f5c4fSSimon Glass return -ENODEV; 223*b24f5c4fSSimon Glass debug("%s: start\n", __func__); 224*b24f5c4fSSimon Glass 225*b24f5c4fSSimon Glass /* Only init once, before relocation */ 226*b24f5c4fSSimon Glass if (gd->flags & GD_FLG_RELOC) 227*b24f5c4fSSimon Glass return 0; 228*b24f5c4fSSimon Glass 229*b24f5c4fSSimon Glass /* 230*b24f5c4fSSimon Glass * Get the memory/io base address to configure every pins. 231*b24f5c4fSSimon Glass * IOBASE is used to configure the mode/pads 232*b24f5c4fSSimon Glass * GPIOBASE is used to configure the direction and default value 233*b24f5c4fSSimon Glass */ 234*b24f5c4fSSimon Glass ret = pch_get_gpio_base(pch, &gpiobase); 235*b24f5c4fSSimon Glass if (ret) { 236*b24f5c4fSSimon Glass debug("%s: invalid GPIOBASE address (%08x)\n", __func__, 237*b24f5c4fSSimon Glass gpiobase); 238*b24f5c4fSSimon Glass return -EINVAL; 239*b24f5c4fSSimon Glass } 240*b24f5c4fSSimon Glass 241*b24f5c4fSSimon Glass conf_count = broadwell_pinctrl_read_configs(dev, conf, 242*b24f5c4fSSimon Glass ARRAY_SIZE(conf)); 243*b24f5c4fSSimon Glass if (conf_count < 0) { 244*b24f5c4fSSimon Glass debug("%s: Cannot read configs: err=%d\n", __func__, ret); 245*b24f5c4fSSimon Glass return conf_count; 246*b24f5c4fSSimon Glass } 247*b24f5c4fSSimon Glass 248*b24f5c4fSSimon Glass /* 249*b24f5c4fSSimon Glass * Assume that pin settings are provided for every pin. Pins not 250*b24f5c4fSSimon Glass * mentioned will get the first config mentioned in the list. 251*b24f5c4fSSimon Glass */ 252*b24f5c4fSSimon Glass ret = broadwell_pinctrl_read_pins(dev, conf, conf_count, gpio_conf, 253*b24f5c4fSSimon Glass MAX_GPIOS); 254*b24f5c4fSSimon Glass if (ret) { 255*b24f5c4fSSimon Glass debug("%s: Cannot read pin settings: err=%d\n", __func__, ret); 256*b24f5c4fSSimon Glass return ret; 257*b24f5c4fSSimon Glass } 258*b24f5c4fSSimon Glass 259*b24f5c4fSSimon Glass regs = (struct pch_lp_gpio_regs *)gpiobase; 260*b24f5c4fSSimon Glass broadwell_pinctrl_commit(regs, conf, gpio_conf, ARRAY_SIZE(conf)); 261*b24f5c4fSSimon Glass 262*b24f5c4fSSimon Glass debug("%s: done\n", __func__); 263*b24f5c4fSSimon Glass 264*b24f5c4fSSimon Glass return 0; 265*b24f5c4fSSimon Glass } 266*b24f5c4fSSimon Glass 267*b24f5c4fSSimon Glass static const struct udevice_id broadwell_pinctrl_match[] = { 268*b24f5c4fSSimon Glass { .compatible = "intel,x86-broadwell-pinctrl", 269*b24f5c4fSSimon Glass .data = X86_SYSCON_PINCONF }, 270*b24f5c4fSSimon Glass { /* sentinel */ } 271*b24f5c4fSSimon Glass }; 272*b24f5c4fSSimon Glass 273*b24f5c4fSSimon Glass U_BOOT_DRIVER(broadwell_pinctrl) = { 274*b24f5c4fSSimon Glass .name = "broadwell_pinctrl", 275*b24f5c4fSSimon Glass .id = UCLASS_SYSCON, 276*b24f5c4fSSimon Glass .of_match = broadwell_pinctrl_match, 277*b24f5c4fSSimon Glass .probe = broadwell_pinctrl_probe, 278*b24f5c4fSSimon Glass }; 279