183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2b24f5c4fSSimon Glass /*
3b24f5c4fSSimon Glass  * Copyright (C) 2016 Google, Inc
4b24f5c4fSSimon Glass  */
5b24f5c4fSSimon Glass 
6b24f5c4fSSimon Glass #include <common.h>
7b24f5c4fSSimon Glass #include <dm.h>
8b24f5c4fSSimon Glass #include <errno.h>
9b24f5c4fSSimon Glass #include <fdtdec.h>
10b24f5c4fSSimon Glass #include <pch.h>
11b24f5c4fSSimon Glass #include <pci.h>
12b24f5c4fSSimon Glass #include <asm/cpu.h>
13b24f5c4fSSimon Glass #include <asm/gpio.h>
14b24f5c4fSSimon Glass #include <asm/io.h>
15b24f5c4fSSimon Glass #include <asm/pci.h>
16b24f5c4fSSimon Glass #include <asm/arch/gpio.h>
17b24f5c4fSSimon Glass #include <dt-bindings/gpio/x86-gpio.h>
18b24f5c4fSSimon Glass #include <dm/pinctrl.h>
19*c692f822SSimon Glass #include <dm/uclass-internal.h>
20b24f5c4fSSimon Glass 
21b24f5c4fSSimon Glass DECLARE_GLOBAL_DATA_PTR;
22b24f5c4fSSimon Glass 
23b24f5c4fSSimon Glass enum {
24b24f5c4fSSimon Glass 	MAX_GPIOS	= 95,
25b24f5c4fSSimon Glass };
26b24f5c4fSSimon Glass 
27b24f5c4fSSimon Glass #define PIRQ_SHIFT	16
28b24f5c4fSSimon Glass #define CONF_MASK	0xffff
29b24f5c4fSSimon Glass 
30b24f5c4fSSimon Glass struct pin_info {
31b24f5c4fSSimon Glass 	int node;
32b24f5c4fSSimon Glass 	int phandle;
33b24f5c4fSSimon Glass 	bool mode_gpio;
34b24f5c4fSSimon Glass 	bool dir_input;
35b24f5c4fSSimon Glass 	bool invert;
36b24f5c4fSSimon Glass 	bool trigger_level;
37b24f5c4fSSimon Glass 	bool output_high;
38b24f5c4fSSimon Glass 	bool sense_disable;
39b24f5c4fSSimon Glass 	bool owner_gpio;
40b24f5c4fSSimon Glass 	bool route_smi;
41b24f5c4fSSimon Glass 	bool irq_enable;
42b24f5c4fSSimon Glass 	bool reset_rsmrst;
43b24f5c4fSSimon Glass 	bool pirq_apic_route;
44b24f5c4fSSimon Glass };
45b24f5c4fSSimon Glass 
broadwell_pinctrl_read_configs(struct udevice * dev,struct pin_info * conf,int max_pins)46b24f5c4fSSimon Glass static int broadwell_pinctrl_read_configs(struct udevice *dev,
47b24f5c4fSSimon Glass 					  struct pin_info *conf, int max_pins)
48b24f5c4fSSimon Glass {
49b24f5c4fSSimon Glass 	const void *blob = gd->fdt_blob;
50b24f5c4fSSimon Glass 	int count = 0;
51b24f5c4fSSimon Glass 	int node;
52b24f5c4fSSimon Glass 
53b24f5c4fSSimon Glass 	debug("%s: starting\n", __func__);
54e160f7d4SSimon Glass 	for (node = fdt_first_subnode(blob, dev_of_offset(dev));
55b24f5c4fSSimon Glass 	     node > 0;
56b24f5c4fSSimon Glass 	     node = fdt_next_subnode(blob, node)) {
57b24f5c4fSSimon Glass 		int phandle = fdt_get_phandle(blob, node);
58b24f5c4fSSimon Glass 
59b24f5c4fSSimon Glass 		if (!phandle)
60b24f5c4fSSimon Glass 			continue;
61b24f5c4fSSimon Glass 		if (count == max_pins)
62b24f5c4fSSimon Glass 			return -ENOSPC;
63b24f5c4fSSimon Glass 
64b24f5c4fSSimon Glass 		/* We've found a new configuration */
65b24f5c4fSSimon Glass 		memset(conf, '\0', sizeof(*conf));
66b24f5c4fSSimon Glass 		conf->node = node;
67b24f5c4fSSimon Glass 		conf->phandle = phandle;
68b24f5c4fSSimon Glass 		conf->mode_gpio = fdtdec_get_bool(blob, node, "mode-gpio");
69b24f5c4fSSimon Glass 		if (fdtdec_get_int(blob, node, "direction", -1) == PIN_INPUT)
70b24f5c4fSSimon Glass 			conf->dir_input = true;
71b24f5c4fSSimon Glass 		conf->invert = fdtdec_get_bool(blob, node, "invert");
72b24f5c4fSSimon Glass 		if (fdtdec_get_int(blob, node, "trigger", -1) == TRIGGER_LEVEL)
73b24f5c4fSSimon Glass 			conf->trigger_level = true;
74b24f5c4fSSimon Glass 		if (fdtdec_get_int(blob, node, "output-value", -1) == 1)
75b24f5c4fSSimon Glass 			conf->output_high = true;
76b24f5c4fSSimon Glass 		conf->sense_disable = fdtdec_get_bool(blob, node,
77b24f5c4fSSimon Glass 						      "sense-disable");
78b24f5c4fSSimon Glass 		if (fdtdec_get_int(blob, node, "owner", -1) == OWNER_GPIO)
79b24f5c4fSSimon Glass 			conf->owner_gpio = true;
80b24f5c4fSSimon Glass 		if (fdtdec_get_int(blob, node, "route", -1) == ROUTE_SMI)
81b24f5c4fSSimon Glass 			conf->route_smi = true;
82b24f5c4fSSimon Glass 		conf->irq_enable = fdtdec_get_bool(blob, node, "irq-enable");
83b24f5c4fSSimon Glass 		conf->reset_rsmrst = fdtdec_get_bool(blob, node,
84b24f5c4fSSimon Glass 						     "reset-rsmrst");
85b24f5c4fSSimon Glass 		if (fdtdec_get_int(blob, node, "pirq-apic", -1) ==
86b24f5c4fSSimon Glass 				PIRQ_APIC_ROUTE)
87b24f5c4fSSimon Glass 			conf->pirq_apic_route = true;
88b24f5c4fSSimon Glass 		debug("config: phandle=%d\n", phandle);
89b24f5c4fSSimon Glass 		count++;
90b24f5c4fSSimon Glass 		conf++;
91b24f5c4fSSimon Glass 	}
92b24f5c4fSSimon Glass 	debug("%s: Found %d configurations\n", __func__, count);
93b24f5c4fSSimon Glass 
94b24f5c4fSSimon Glass 	return count;
95b24f5c4fSSimon Glass }
96b24f5c4fSSimon Glass 
broadwell_pinctrl_lookup_phandle(struct pin_info * conf,int conf_count,int phandle)97b24f5c4fSSimon Glass static int broadwell_pinctrl_lookup_phandle(struct pin_info *conf,
98b24f5c4fSSimon Glass 					    int conf_count, int phandle)
99b24f5c4fSSimon Glass {
100b24f5c4fSSimon Glass 	int i;
101b24f5c4fSSimon Glass 
102b24f5c4fSSimon Glass 	for (i = 0; i < conf_count; i++) {
103b24f5c4fSSimon Glass 		if (conf[i].phandle == phandle)
104b24f5c4fSSimon Glass 			return i;
105b24f5c4fSSimon Glass 	}
106b24f5c4fSSimon Glass 
107b24f5c4fSSimon Glass 	return -ENOENT;
108b24f5c4fSSimon Glass }
109b24f5c4fSSimon Glass 
broadwell_pinctrl_read_pins(struct udevice * dev,struct pin_info * conf,int conf_count,int gpio_conf[],int num_gpios)110b24f5c4fSSimon Glass static int broadwell_pinctrl_read_pins(struct udevice *dev,
111b24f5c4fSSimon Glass 		struct pin_info *conf, int conf_count, int gpio_conf[],
112b24f5c4fSSimon Glass 		int num_gpios)
113b24f5c4fSSimon Glass {
114b24f5c4fSSimon Glass 	const void *blob = gd->fdt_blob;
115b24f5c4fSSimon Glass 	int count = 0;
116b24f5c4fSSimon Glass 	int node;
117b24f5c4fSSimon Glass 
118e160f7d4SSimon Glass 	for (node = fdt_first_subnode(blob, dev_of_offset(dev));
119b24f5c4fSSimon Glass 	     node > 0;
120b24f5c4fSSimon Glass 	     node = fdt_next_subnode(blob, node)) {
121b24f5c4fSSimon Glass 		int len, i;
122b24f5c4fSSimon Glass 		const u32 *prop = fdt_getprop(blob, node, "config", &len);
123b24f5c4fSSimon Glass 
124b24f5c4fSSimon Glass 		if (!prop)
125b24f5c4fSSimon Glass 			continue;
126b24f5c4fSSimon Glass 
127b24f5c4fSSimon Glass 		/* There are three cells per pin */
128b24f5c4fSSimon Glass 		count = len / (sizeof(u32) * 3);
129b24f5c4fSSimon Glass 		debug("Found %d GPIOs to configure\n", count);
130b24f5c4fSSimon Glass 		for (i = 0; i < count; i++) {
131b24f5c4fSSimon Glass 			uint gpio = fdt32_to_cpu(prop[i * 3]);
132b24f5c4fSSimon Glass 			uint phandle = fdt32_to_cpu(prop[i * 3 + 1]);
133b24f5c4fSSimon Glass 			int val;
134b24f5c4fSSimon Glass 
135b24f5c4fSSimon Glass 			if (gpio >= num_gpios) {
136b24f5c4fSSimon Glass 				debug("%s: GPIO %d out of range\n", __func__,
137b24f5c4fSSimon Glass 				      gpio);
138b24f5c4fSSimon Glass 				return -EDOM;
139b24f5c4fSSimon Glass 			}
140b24f5c4fSSimon Glass 			val = broadwell_pinctrl_lookup_phandle(conf, conf_count,
141b24f5c4fSSimon Glass 							       phandle);
142b24f5c4fSSimon Glass 			if (val < 0) {
143b24f5c4fSSimon Glass 				debug("%s: Cannot find phandle %d\n", __func__,
144b24f5c4fSSimon Glass 				      phandle);
145b24f5c4fSSimon Glass 				return -EINVAL;
146b24f5c4fSSimon Glass 			}
147b24f5c4fSSimon Glass 			gpio_conf[gpio] = val |
148b24f5c4fSSimon Glass 				fdt32_to_cpu(prop[i * 3 + 2]) << PIRQ_SHIFT;
149b24f5c4fSSimon Glass 		}
150b24f5c4fSSimon Glass 	}
151b24f5c4fSSimon Glass 
152b24f5c4fSSimon Glass 	return 0;
153b24f5c4fSSimon Glass }
154b24f5c4fSSimon Glass 
broadwell_pinctrl_commit(struct pch_lp_gpio_regs * regs,struct pin_info * pin_info,int gpio_conf[],int count)155b24f5c4fSSimon Glass static void broadwell_pinctrl_commit(struct pch_lp_gpio_regs *regs,
156b24f5c4fSSimon Glass 				     struct pin_info *pin_info,
157b24f5c4fSSimon Glass 				     int gpio_conf[], int count)
158b24f5c4fSSimon Glass {
159b24f5c4fSSimon Glass 	u32 owner_gpio[GPIO_BANKS] = {0};
160b24f5c4fSSimon Glass 	u32 route_smi[GPIO_BANKS] = {0};
161b24f5c4fSSimon Glass 	u32 irq_enable[GPIO_BANKS] = {0};
162b24f5c4fSSimon Glass 	u32 reset_rsmrst[GPIO_BANKS] = {0};
163b24f5c4fSSimon Glass 	u32 pirq2apic = 0;
164b24f5c4fSSimon Glass 	int set, bit, gpio = 0;
165b24f5c4fSSimon Glass 
166b24f5c4fSSimon Glass 	for (gpio = 0; gpio < MAX_GPIOS; gpio++) {
167b24f5c4fSSimon Glass 		int confnum = gpio_conf[gpio] & CONF_MASK;
168b24f5c4fSSimon Glass 		struct pin_info *pin = &pin_info[confnum];
169b24f5c4fSSimon Glass 		u32 val;
170b24f5c4fSSimon Glass 
171b24f5c4fSSimon Glass 		val = pin->mode_gpio << CONFA_MODE_SHIFT |
172b24f5c4fSSimon Glass 			pin->dir_input << CONFA_DIR_SHIFT |
173b24f5c4fSSimon Glass 			pin->invert << CONFA_INVERT_SHIFT |
174b24f5c4fSSimon Glass 			pin->trigger_level << CONFA_TRIGGER_SHIFT |
175b24f5c4fSSimon Glass 			pin->output_high << CONFA_OUTPUT_SHIFT;
176b24f5c4fSSimon Glass 		outl(val, &regs->config[gpio].conf_a);
177b24f5c4fSSimon Glass 		outl(pin->sense_disable << CONFB_SENSE_SHIFT,
178b24f5c4fSSimon Glass 		     &regs->config[gpio].conf_b);
179b24f5c4fSSimon Glass 
180b24f5c4fSSimon Glass 		/* Determine set and bit based on GPIO number */
181b24f5c4fSSimon Glass 		set = gpio / GPIO_PER_BANK;
182b24f5c4fSSimon Glass 		bit = gpio % GPIO_PER_BANK;
183b24f5c4fSSimon Glass 
184b24f5c4fSSimon Glass 		/* Apply settings to set specific bits */
185b24f5c4fSSimon Glass 		owner_gpio[set] |= pin->owner_gpio << bit;
186b24f5c4fSSimon Glass 		route_smi[set] |= pin->route_smi << bit;
187b24f5c4fSSimon Glass 		irq_enable[set] |= pin->irq_enable << bit;
188b24f5c4fSSimon Glass 		reset_rsmrst[set] |= pin->reset_rsmrst << bit;
189b24f5c4fSSimon Glass 
190b24f5c4fSSimon Glass 		/* PIRQ to IO-APIC map */
191b24f5c4fSSimon Glass 		if (pin->pirq_apic_route)
192b24f5c4fSSimon Glass 			pirq2apic |= gpio_conf[gpio] >> PIRQ_SHIFT;
193b24f5c4fSSimon Glass 		debug("gpio %d: conf %d, mode_gpio %d, dir_input %d, output_high %d\n",
194b24f5c4fSSimon Glass 		      gpio, confnum, pin->mode_gpio, pin->dir_input,
195b24f5c4fSSimon Glass 		      pin->output_high);
196b24f5c4fSSimon Glass 	}
197b24f5c4fSSimon Glass 
198b24f5c4fSSimon Glass 	for (set = 0; set < GPIO_BANKS; set++) {
199b24f5c4fSSimon Glass 		outl(owner_gpio[set], &regs->own[set]);
200b24f5c4fSSimon Glass 		outl(route_smi[set], &regs->gpi_route[set]);
201b24f5c4fSSimon Glass 		outl(irq_enable[set], &regs->gpi_ie[set]);
202b24f5c4fSSimon Glass 		outl(reset_rsmrst[set], &regs->rst_sel[set]);
203b24f5c4fSSimon Glass 	}
204b24f5c4fSSimon Glass 
205b24f5c4fSSimon Glass 	outl(pirq2apic, &regs->pirq_to_ioxapic);
206b24f5c4fSSimon Glass }
207b24f5c4fSSimon Glass 
broadwell_pinctrl_probe(struct udevice * dev)208b24f5c4fSSimon Glass static int broadwell_pinctrl_probe(struct udevice *dev)
209b24f5c4fSSimon Glass {
210b24f5c4fSSimon Glass 	struct pch_lp_gpio_regs *regs;
211b24f5c4fSSimon Glass 	struct pin_info conf[12];
212b24f5c4fSSimon Glass 	int gpio_conf[MAX_GPIOS];
213b24f5c4fSSimon Glass 	struct udevice *pch;
214b24f5c4fSSimon Glass 	int conf_count;
215b24f5c4fSSimon Glass 	u32 gpiobase;
216b24f5c4fSSimon Glass 	int ret;
217b24f5c4fSSimon Glass 
218*c692f822SSimon Glass 	ret = uclass_find_first_device(UCLASS_PCH, &pch);
219b24f5c4fSSimon Glass 	if (ret)
220b24f5c4fSSimon Glass 		return ret;
221b24f5c4fSSimon Glass 	if (!pch)
222b24f5c4fSSimon Glass 		return -ENODEV;
223b24f5c4fSSimon Glass 	debug("%s: start\n", __func__);
224b24f5c4fSSimon Glass 
225b24f5c4fSSimon Glass 	/* Only init once, before relocation */
226b24f5c4fSSimon Glass 	if (gd->flags & GD_FLG_RELOC)
227b24f5c4fSSimon Glass 		return 0;
228b24f5c4fSSimon Glass 
229b24f5c4fSSimon Glass 	/*
230b24f5c4fSSimon Glass 	 * Get the memory/io base address to configure every pins.
231b24f5c4fSSimon Glass 	 * IOBASE is used to configure the mode/pads
232b24f5c4fSSimon Glass 	 * GPIOBASE is used to configure the direction and default value
233b24f5c4fSSimon Glass 	 */
234b24f5c4fSSimon Glass 	ret = pch_get_gpio_base(pch, &gpiobase);
235b24f5c4fSSimon Glass 	if (ret) {
236b24f5c4fSSimon Glass 		debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
237b24f5c4fSSimon Glass 		      gpiobase);
238b24f5c4fSSimon Glass 		return -EINVAL;
239b24f5c4fSSimon Glass 	}
240b24f5c4fSSimon Glass 
241b24f5c4fSSimon Glass 	conf_count = broadwell_pinctrl_read_configs(dev, conf,
242b24f5c4fSSimon Glass 						    ARRAY_SIZE(conf));
243b24f5c4fSSimon Glass 	if (conf_count < 0) {
244b24f5c4fSSimon Glass 		debug("%s: Cannot read configs: err=%d\n", __func__, ret);
245b24f5c4fSSimon Glass 		return conf_count;
246b24f5c4fSSimon Glass 	}
247b24f5c4fSSimon Glass 
248b24f5c4fSSimon Glass 	/*
249b24f5c4fSSimon Glass 	 * Assume that pin settings are provided for every pin. Pins not
250b24f5c4fSSimon Glass 	 * mentioned will get the first config mentioned in the list.
251b24f5c4fSSimon Glass 	 */
252b24f5c4fSSimon Glass 	ret = broadwell_pinctrl_read_pins(dev, conf, conf_count, gpio_conf,
253b24f5c4fSSimon Glass 					  MAX_GPIOS);
254b24f5c4fSSimon Glass 	if (ret) {
255b24f5c4fSSimon Glass 		debug("%s: Cannot read pin settings: err=%d\n", __func__, ret);
256b24f5c4fSSimon Glass 		return ret;
257b24f5c4fSSimon Glass 	}
258b24f5c4fSSimon Glass 
259b24f5c4fSSimon Glass 	regs = (struct pch_lp_gpio_regs *)gpiobase;
260b24f5c4fSSimon Glass 	broadwell_pinctrl_commit(regs, conf, gpio_conf, ARRAY_SIZE(conf));
261b24f5c4fSSimon Glass 
262b24f5c4fSSimon Glass 	debug("%s: done\n", __func__);
263b24f5c4fSSimon Glass 
264b24f5c4fSSimon Glass 	return 0;
265b24f5c4fSSimon Glass }
266b24f5c4fSSimon Glass 
267b24f5c4fSSimon Glass static const struct udevice_id broadwell_pinctrl_match[] = {
268b24f5c4fSSimon Glass 	{ .compatible = "intel,x86-broadwell-pinctrl",
269b24f5c4fSSimon Glass 		.data = X86_SYSCON_PINCONF },
270b24f5c4fSSimon Glass 	{ /* sentinel */ }
271b24f5c4fSSimon Glass };
272b24f5c4fSSimon Glass 
273b24f5c4fSSimon Glass U_BOOT_DRIVER(broadwell_pinctrl) = {
274b24f5c4fSSimon Glass 	.name = "broadwell_pinctrl",
275b24f5c4fSSimon Glass 	.id = UCLASS_SYSCON,
276b24f5c4fSSimon Glass 	.of_match = broadwell_pinctrl_match,
277b24f5c4fSSimon Glass 	.probe = broadwell_pinctrl_probe,
278b24f5c4fSSimon Glass };
279