1 /* 2 * Copyright (c) 2016 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <pch.h> 10 #include <asm/cpu.h> 11 #include <asm/gpio.h> 12 #include <asm/i8259.h> 13 #include <asm/intel_regs.h> 14 #include <asm/io.h> 15 #include <asm/ioapic.h> 16 #include <asm/lpc_common.h> 17 #include <asm/pch_common.h> 18 #include <asm/arch/cpu.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/iomap.h> 21 #include <asm/arch/pch.h> 22 #include <asm/arch/pm.h> 23 #include <asm/arch/rcb.h> 24 #include <asm/arch/spi.h> 25 26 #define BIOS_CTRL 0xdc 27 28 bool cpu_is_ult(void) 29 { 30 u32 fm = cpu_get_family_model(); 31 32 return fm == BROADWELL_FAMILY_ULT || fm == HASWELL_FAMILY_ULT; 33 } 34 35 static int broadwell_pch_early_init(struct udevice *dev) 36 { 37 struct gpio_desc desc; 38 struct udevice *bus; 39 pci_dev_t bdf; 40 int ret; 41 42 dm_pci_write_config32(dev, PCH_RCBA, RCB_BASE_ADDRESS | 1); 43 44 dm_pci_write_config32(dev, PMBASE, ACPI_BASE_ADDRESS | 1); 45 dm_pci_write_config8(dev, ACPI_CNTL, ACPI_EN); 46 dm_pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDRESS | 1); 47 dm_pci_write_config8(dev, GPIO_CNTL, GPIO_EN); 48 49 /* Enable IOAPIC */ 50 writew(0x1000, RCB_REG(OIC)); 51 /* Read back for posted write */ 52 readw(RCB_REG(OIC)); 53 54 /* Set HPET address and enable it */ 55 clrsetbits_le32(RCB_REG(HPTC), 3, 1 << 7); 56 /* Read back for posted write */ 57 readl(RCB_REG(HPTC)); 58 /* Enable HPET to start counter */ 59 setbits_le32(HPET_BASE_ADDRESS + 0x10, 1 << 0); 60 61 setbits_le32(RCB_REG(GCS), 1 << 5); 62 63 /* 64 * Enable PP3300_AUTOBAHN_EN after initial GPIO setup 65 * to prevent possible brownout. This will cause the GPIOs to be set 66 * up if it has not been done already. 67 */ 68 ret = gpio_request_by_name(dev, "power-enable-gpio", 0, &desc, 69 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); 70 if (ret) 71 return ret; 72 73 /* 8.14 Additional PCI Express Programming Steps, step #1 */ 74 bdf = PCI_BDF(0, 0x1c, 0); 75 bus = pci_get_controller(dev); 76 pci_bus_clrset_config32(bus, bdf, 0xf4, 0x60, 0); 77 pci_bus_clrset_config32(bus, bdf, 0xf4, 0x80, 0x80); 78 pci_bus_clrset_config32(bus, bdf, 0xe2, 0x30, 0x30); 79 80 return 0; 81 } 82 83 static void pch_misc_init(struct udevice *dev) 84 { 85 /* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */ 86 dm_pci_clrset_config8(dev, GEN_PMCON_3, 3 << 4 | 1 << 10, 87 1 << 3 | 1 << 11 | 1 << 12); 88 /* Prepare sleep mode */ 89 clrsetio_32(ACPI_BASE_ADDRESS + PM1_CNT, SLP_TYP, SCI_EN); 90 91 /* Setup NMI on errors, disable SERR */ 92 clrsetio_8(0x61, 0xf0, 1 << 2); 93 /* Disable NMI sources */ 94 setio_8(0x70, 1 << 7); 95 /* Indicate DRAM init done for MRC */ 96 dm_pci_clrset_config8(dev, GEN_PMCON_2, 0, 1 << 7); 97 98 /* Clear status bits to prevent unexpected wake */ 99 setbits_le32(RCB_REG(0x3310), 0x0000002f); 100 clrsetbits_le32(RCB_REG(0x3f02), 0x0000000f, 0); 101 /* Enable PCIe Relaxed Order */ 102 setbits_le32(RCB_REG(0x2314), 1 << 31 | 1 << 7); 103 setbits_le32(RCB_REG(0x1114), 1 << 15 | 1 << 14); 104 /* Setup SERIRQ, enable continuous mode */ 105 dm_pci_clrset_config8(dev, SERIRQ_CNTL, 0, 1 << 7 | 1 << 6); 106 }; 107 108 static void pch_enable_ioapic(void) 109 { 110 u32 reg32; 111 112 /* Make sure this is a unique ID within system */ 113 io_apic_set_id(0x04); 114 115 /* affirm full set of redirection table entries ("write once") */ 116 reg32 = io_apic_read(0x01); 117 118 /* PCH-LP has 39 redirection entries */ 119 reg32 &= ~0x00ff0000; 120 reg32 |= 0x00270000; 121 122 io_apic_write(0x01, reg32); 123 124 /* 125 * Select Boot Configuration register (0x03) and 126 * use Processor System Bus (0x01) to deliver interrupts. 127 */ 128 io_apic_write(0x03, 0x01); 129 } 130 131 /* Enable all requested GPE */ 132 void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4) 133 { 134 outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0)); 135 outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32)); 136 outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_94_64)); 137 outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); 138 } 139 140 /* 141 * Enable GPIO SMI events - it would be good to put this in the GPIO driver 142 * but it would need a new driver operation. 143 */ 144 int enable_alt_smi(struct udevice *pch, u32 mask) 145 { 146 struct pch_lp_gpio_regs *regs; 147 u32 gpiobase; 148 int ret; 149 150 ret = pch_get_gpio_base(pch, &gpiobase); 151 if (ret) { 152 debug("%s: invalid GPIOBASE address (%08x)\n", __func__, 153 gpiobase); 154 return -EINVAL; 155 } 156 157 regs = (struct pch_lp_gpio_regs *)gpiobase; 158 setio_32(regs->alt_gpi_smi_en, mask); 159 160 return 0; 161 } 162 163 static int pch_power_options(struct udevice *dev) 164 { 165 int pwr_on_after_power_fail = MAINBOARD_POWER_OFF; 166 const char *state; 167 u32 enable[4]; 168 u16 reg16; 169 int ret; 170 171 dm_pci_read_config16(dev, GEN_PMCON_3, ®16); 172 reg16 &= 0xfffe; 173 switch (pwr_on_after_power_fail) { 174 case MAINBOARD_POWER_OFF: 175 reg16 |= 1; 176 state = "off"; 177 break; 178 case MAINBOARD_POWER_ON: 179 reg16 &= ~1; 180 state = "on"; 181 break; 182 case MAINBOARD_POWER_KEEP: 183 reg16 &= ~1; 184 state = "state keep"; 185 break; 186 default: 187 state = "undefined"; 188 } 189 dm_pci_write_config16(dev, GEN_PMCON_3, reg16); 190 debug("Set power %s after power failure.\n", state); 191 192 /* GPE setup based on device tree configuration */ 193 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), 194 "intel,gpe0-en", enable, ARRAY_SIZE(enable)); 195 if (ret) 196 return -EINVAL; 197 enable_all_gpe(enable[0], enable[1], enable[2], enable[3]); 198 199 /* SMI setup based on device tree configuration */ 200 enable_alt_smi(dev, fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 201 "intel,alt-gp-smi-enable", 0)); 202 203 return 0; 204 } 205 206 /* Magic register settings for power management */ 207 static void pch_pm_init_magic(struct udevice *dev) 208 { 209 dm_pci_write_config8(dev, 0xa9, 0x46); 210 clrbits_le32(RCB_REG(0x232c), 1), 211 setbits_le32(RCB_REG(0x1100), 0x0000c13f); 212 clrsetbits_le32(RCB_REG(0x2320), 0x60, 0x10); 213 writel(0x00012fff, RCB_REG(0x3314)); 214 clrsetbits_le32(RCB_REG(0x3318), 0x000f0330, 0x0dcf0400); 215 writel(0x04000000, RCB_REG(0x3324)); 216 writel(0x00041400, RCB_REG(0x3368)); 217 writel(0x3f8ddbff, RCB_REG(0x3388)); 218 writel(0x00007001, RCB_REG(0x33ac)); 219 writel(0x00181900, RCB_REG(0x33b0)); 220 writel(0x00060A00, RCB_REG(0x33c0)); 221 writel(0x06200840, RCB_REG(0x33d0)); 222 writel(0x01010101, RCB_REG(0x3a28)); 223 writel(0x040c0404, RCB_REG(0x3a2c)); 224 writel(0x9000000a, RCB_REG(0x3a9c)); 225 writel(0x03808033, RCB_REG(0x2b1c)); 226 writel(0x80000009, RCB_REG(0x2b34)); 227 writel(0x022ddfff, RCB_REG(0x3348)); 228 writel(0x00000001, RCB_REG(0x334c)); 229 writel(0x0001c000, RCB_REG(0x3358)); 230 writel(0x3f8ddbff, RCB_REG(0x3380)); 231 writel(0x0001c7e1, RCB_REG(0x3384)); 232 writel(0x0001c7e1, RCB_REG(0x338c)); 233 writel(0x0001c000, RCB_REG(0x3398)); 234 writel(0x00181900, RCB_REG(0x33a8)); 235 writel(0x00080000, RCB_REG(0x33dc)); 236 writel(0x00000001, RCB_REG(0x33e0)); 237 writel(0x0000040c, RCB_REG(0x3a20)); 238 writel(0x01010101, RCB_REG(0x3a24)); 239 writel(0x01010101, RCB_REG(0x3a30)); 240 dm_pci_clrset_config32(dev, 0xac, 0x00200000, 0); 241 setbits_le32(RCB_REG(0x0410), 0x00000003); 242 setbits_le32(RCB_REG(0x2618), 0x08000000); 243 setbits_le32(RCB_REG(0x2300), 0x00000002); 244 setbits_le32(RCB_REG(0x2600), 0x00000008); 245 writel(0x00007001, RCB_REG(0x33b4)); 246 writel(0x022ddfff, RCB_REG(0x3350)); 247 writel(0x00000001, RCB_REG(0x3354)); 248 /* Power Optimizer */ 249 setbits_le32(RCB_REG(0x33d4), 0x08000000); 250 /* 251 * This stops the LCD from turning on: 252 * setbits_le32(RCB_REG(0x33c8), 0x08000080); 253 */ 254 writel(0x0000883c, RCB_REG(0x2b10)); 255 writel(0x1e0a4616, RCB_REG(0x2b14)); 256 writel(0x40000005, RCB_REG(0x2b24)); 257 writel(0x0005db01, RCB_REG(0x2b20)); 258 writel(0x05145005, RCB_REG(0x3a80)); 259 writel(0x00001005, RCB_REG(0x3a84)); 260 setbits_le32(RCB_REG(0x33d4), 0x2fff2fb1); 261 setbits_le32(RCB_REG(0x33c8), 0x00008000); 262 }; 263 264 static int pch_type(struct udevice *dev) 265 { 266 u16 type; 267 268 dm_pci_read_config16(dev, PCI_DEVICE_ID, &type); 269 270 return type; 271 } 272 273 /* Return 1 if PCH type is WildcatPoint */ 274 static int pch_is_wpt(struct udevice *dev) 275 { 276 return ((pch_type(dev) & 0xfff0) == 0x9cc0) ? 1 : 0; 277 } 278 279 /* Return 1 if PCH type is WildcatPoint ULX */ 280 static int pch_is_wpt_ulx(struct udevice *dev) 281 { 282 u16 lpcid = pch_type(dev); 283 284 switch (lpcid) { 285 case PCH_WPT_BDW_Y_SAMPLE: 286 case PCH_WPT_BDW_Y_PREMIUM: 287 case PCH_WPT_BDW_Y_BASE: 288 return 1; 289 } 290 291 return 0; 292 } 293 294 static u32 pch_read_soft_strap(int id) 295 { 296 clrbits_le32(SPI_REG(SPIBAR_FDOC), 0x00007ffc); 297 setbits_le32(SPI_REG(SPIBAR_FDOC), 0x00004000 | id * 4); 298 299 return readl(SPI_REG(SPIBAR_FDOD)); 300 } 301 302 static void pch_enable_mphy(struct udevice *dev) 303 { 304 u32 data_and = 0xffffffff; 305 u32 data_or = (1 << 14) | (1 << 13) | (1 << 12); 306 307 data_or |= (1 << 0); 308 if (pch_is_wpt(dev)) { 309 data_and &= ~((1 << 7) | (1 << 6) | (1 << 3)); 310 data_or |= (1 << 5) | (1 << 4); 311 312 if (pch_is_wpt_ulx(dev)) { 313 /* Check if SATA and USB3 MPHY are enabled */ 314 u32 strap19 = pch_read_soft_strap(19); 315 strap19 &= ((1 << 31) | (1 << 30)); 316 strap19 >>= 30; 317 if (strap19 == 3) { 318 data_or |= (1 << 3); 319 debug("Enable ULX MPHY PG control in single domain\n"); 320 } else if (strap19 == 0) { 321 debug("Enable ULX MPHY PG control in split domains\n"); 322 } else { 323 debug("Invalid PCH Soft Strap 19 configuration\n"); 324 } 325 } else { 326 data_or |= (1 << 3); 327 } 328 } 329 330 pch_iobp_update(0xCF000000, data_and, data_or); 331 } 332 333 static void pch_init_deep_sx(bool deep_sx_enable_ac, bool deep_sx_enable_dc) 334 { 335 if (deep_sx_enable_ac) { 336 setbits_le32(RCB_REG(DEEP_S3_POL), DEEP_S3_EN_AC); 337 setbits_le32(RCB_REG(DEEP_S5_POL), DEEP_S5_EN_AC); 338 } 339 340 if (deep_sx_enable_dc) { 341 setbits_le32(RCB_REG(DEEP_S3_POL), DEEP_S3_EN_DC); 342 setbits_le32(RCB_REG(DEEP_S5_POL), DEEP_S5_EN_DC); 343 } 344 345 if (deep_sx_enable_ac || deep_sx_enable_dc) { 346 setbits_le32(RCB_REG(DEEP_SX_CONFIG), 347 DEEP_SX_WAKE_PIN_EN | DEEP_SX_GP27_PIN_EN); 348 } 349 } 350 351 /* Power Management init */ 352 static void pch_pm_init(struct udevice *dev) 353 { 354 debug("PCH PM init\n"); 355 356 pch_init_deep_sx(false, false); 357 pch_enable_mphy(dev); 358 pch_pm_init_magic(dev); 359 360 if (pch_is_wpt(dev)) { 361 setbits_le32(RCB_REG(0x33e0), 1 << 4 | 1 << 1); 362 setbits_le32(RCB_REG(0x2b1c), 1 << 22 | 1 << 14 | 1 << 13); 363 writel(0x16bf0002, RCB_REG(0x33e4)); 364 setbits_le32(RCB_REG(0x33e4), 0x1); 365 } 366 367 pch_iobp_update(0xCA000000, ~0UL, 0x00000009); 368 369 /* Set RCBA 0x2b1c[29]=1 if DSP disabled */ 370 if (readl(RCB_REG(FD)) & PCH_DISABLE_ADSPD) 371 setbits_le32(RCB_REG(0x2b1c), 1 << 29); 372 } 373 374 static void pch_cg_init(struct udevice *dev) 375 { 376 struct udevice *bus = pci_get_controller(dev); 377 u32 reg32; 378 u16 reg16; 379 ulong val; 380 381 /* DMI */ 382 setbits_le32(RCB_REG(0x2234), 0xf); 383 384 dm_pci_read_config16(dev, GEN_PMCON_1, ®16); 385 reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ 386 if (pch_is_wpt(dev)) 387 reg16 &= ~(1 << 11); 388 else 389 reg16 |= 1 << 11; 390 reg16 |= 1 << 5 | 1 << 6 | 1 << 7 | 1 << 12; 391 reg16 |= 1 << 2; /* PCI CLKRUN# Enable */ 392 dm_pci_write_config16(dev, GEN_PMCON_1, reg16); 393 394 /* 395 * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1 396 * RCBA + 0x2614[23:16] = 0x20 397 * RCBA + 0x2614[30:28] = 0x0 398 * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) 399 */ 400 clrsetbits_le32(RCB_REG(0x2614), 0x64ff0000, 0x0a206500); 401 402 /* Check for 0:2.0@0x08 >= 0x0b */ 403 pci_bus_read_config(bus, PCI_BDF(0, 0x2, 0), 0x8, &val, PCI_SIZE_8); 404 if (pch_is_wpt(dev) || val >= 0x0b) 405 setbits_le32(RCB_REG(0x2614), 1 << 26); 406 407 setbits_le32(RCB_REG(0x900), 0x0000031f); 408 409 reg32 = readl(RCB_REG(CG)); 410 if (readl(RCB_REG(0x3454)) & (1 << 4)) 411 reg32 &= ~(1 << 29); /* LPC Dynamic */ 412 else 413 reg32 |= (1 << 29); /* LPC Dynamic */ 414 reg32 |= 1 << 31; /* LP LPC */ 415 reg32 |= 1 << 30; /* LP BLA */ 416 if (readl(RCB_REG(0x3454)) & (1 << 4)) 417 reg32 &= ~(1 << 29); 418 else 419 reg32 |= 1 << 29; 420 reg32 |= 1 << 28; /* GPIO Dynamic */ 421 reg32 |= 1 << 27; /* HPET Dynamic */ 422 reg32 |= 1 << 26; /* Generic Platform Event Clock */ 423 if (readl(RCB_REG(BUC)) & PCH_DISABLE_GBE) 424 reg32 |= 1 << 23; /* GbE Static */ 425 if (readl(RCB_REG(FD)) & PCH_DISABLE_HD_AUDIO) 426 reg32 |= 1 << 21; /* HDA Static */ 427 reg32 |= 1 << 22; /* HDA Dynamic */ 428 writel(reg32, RCB_REG(CG)); 429 430 /* PCH-LP LPC */ 431 if (pch_is_wpt(dev)) 432 clrsetbits_le32(RCB_REG(0x3434), 0x1f, 0x17); 433 else 434 setbits_le32(RCB_REG(0x3434), 0x7); 435 436 /* SPI */ 437 setbits_le32(RCB_REG(0x38c0), 0x3c07); 438 439 pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); 440 } 441 442 static void systemagent_init(void) 443 { 444 /* Enable Power Aware Interrupt Routing */ 445 clrsetbits_8(MCHBAR_REG(MCH_PAIR), 0x7, 0x4); /* Fixed Priority */ 446 447 /* 448 * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU 449 * that BIOS has initialized memory and power management 450 */ 451 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3); 452 debug("Set BIOS_RESET_CPL\n"); 453 454 /* Configure turbo power limits 1ms after reset complete bit */ 455 mdelay(1); 456 457 cpu_set_power_limits(28); 458 } 459 460 static int broadwell_pch_init(struct udevice *dev) 461 { 462 int ret; 463 464 /* Enable upper 128 bytes of CMOS */ 465 setbits_le32(RCB_REG(RC), 1 << 2); 466 467 /* 468 * TODO: TCO timer halt - this hangs 469 * setio_16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT); 470 */ 471 472 /* Disable unused device (always) */ 473 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS); 474 475 pch_misc_init(dev); 476 477 /* Interrupt configuration */ 478 pch_enable_ioapic(); 479 480 /* Initialize power management */ 481 ret = pch_power_options(dev); 482 if (ret) 483 return ret; 484 pch_pm_init(dev); 485 pch_cg_init(dev); 486 systemagent_init(); 487 488 return 0; 489 } 490 491 static int broadwell_pch_probe(struct udevice *dev) 492 { 493 if (!(gd->flags & GD_FLG_RELOC)) 494 return broadwell_pch_early_init(dev); 495 else 496 return broadwell_pch_init(dev); 497 } 498 499 static int broadwell_pch_get_spi_base(struct udevice *dev, ulong *sbasep) 500 { 501 u32 rcba; 502 503 dm_pci_read_config32(dev, PCH_RCBA, &rcba); 504 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ 505 rcba = rcba & 0xffffc000; 506 *sbasep = rcba + 0x3800; 507 508 return 0; 509 } 510 511 static int broadwell_set_spi_protect(struct udevice *dev, bool protect) 512 { 513 return lpc_set_spi_protect(dev, BIOS_CTRL, protect); 514 } 515 516 static int broadwell_get_gpio_base(struct udevice *dev, u32 *gbasep) 517 { 518 dm_pci_read_config32(dev, GPIO_BASE, gbasep); 519 *gbasep &= PCI_BASE_ADDRESS_IO_MASK; 520 521 return 0; 522 } 523 524 static const struct pch_ops broadwell_pch_ops = { 525 .get_spi_base = broadwell_pch_get_spi_base, 526 .set_spi_protect = broadwell_set_spi_protect, 527 .get_gpio_base = broadwell_get_gpio_base, 528 }; 529 530 static const struct udevice_id broadwell_pch_ids[] = { 531 { .compatible = "intel,broadwell-pch" }, 532 { } 533 }; 534 535 U_BOOT_DRIVER(broadwell_pch) = { 536 .name = "broadwell_pch", 537 .id = UCLASS_PCH, 538 .of_match = broadwell_pch_ids, 539 .probe = broadwell_pch_probe, 540 .ops = &broadwell_pch_ops, 541 }; 542