1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016 Google, Inc 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <pch.h> 9 #include <asm/cpu.h> 10 #include <asm/gpio.h> 11 #include <asm/i8259.h> 12 #include <asm/intel_regs.h> 13 #include <asm/io.h> 14 #include <asm/ioapic.h> 15 #include <asm/lpc_common.h> 16 #include <asm/pch_common.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/gpio.h> 19 #include <asm/arch/iomap.h> 20 #include <asm/arch/pch.h> 21 #include <asm/arch/pm.h> 22 #include <asm/arch/rcb.h> 23 #include <asm/arch/spi.h> 24 25 #define BIOS_CTRL 0xdc 26 27 bool cpu_is_ult(void) 28 { 29 u32 fm = cpu_get_family_model(); 30 31 return fm == BROADWELL_FAMILY_ULT || fm == HASWELL_FAMILY_ULT; 32 } 33 34 static int broadwell_pch_early_init(struct udevice *dev) 35 { 36 struct gpio_desc desc; 37 struct udevice *bus; 38 pci_dev_t bdf; 39 int ret; 40 41 dm_pci_write_config32(dev, PCH_RCBA, RCB_BASE_ADDRESS | 1); 42 43 dm_pci_write_config32(dev, PMBASE, ACPI_BASE_ADDRESS | 1); 44 dm_pci_write_config8(dev, ACPI_CNTL, ACPI_EN); 45 dm_pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDRESS | 1); 46 dm_pci_write_config8(dev, GPIO_CNTL, GPIO_EN); 47 48 /* Enable IOAPIC */ 49 writew(0x1000, RCB_REG(OIC)); 50 /* Read back for posted write */ 51 readw(RCB_REG(OIC)); 52 53 /* Set HPET address and enable it */ 54 clrsetbits_le32(RCB_REG(HPTC), 3, 1 << 7); 55 /* Read back for posted write */ 56 readl(RCB_REG(HPTC)); 57 /* Enable HPET to start counter */ 58 setbits_le32(HPET_BASE_ADDRESS + 0x10, 1 << 0); 59 60 setbits_le32(RCB_REG(GCS), 1 << 5); 61 62 /* 63 * Enable PP3300_AUTOBAHN_EN after initial GPIO setup 64 * to prevent possible brownout. This will cause the GPIOs to be set 65 * up if it has not been done already. 66 */ 67 ret = gpio_request_by_name(dev, "power-enable-gpio", 0, &desc, 68 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); 69 if (ret) 70 return ret; 71 72 /* 8.14 Additional PCI Express Programming Steps, step #1 */ 73 bdf = PCI_BDF(0, 0x1c, 0); 74 bus = pci_get_controller(dev); 75 pci_bus_clrset_config32(bus, bdf, 0xf4, 0x60, 0); 76 pci_bus_clrset_config32(bus, bdf, 0xf4, 0x80, 0x80); 77 pci_bus_clrset_config32(bus, bdf, 0xe2, 0x30, 0x30); 78 79 return 0; 80 } 81 82 static void pch_misc_init(struct udevice *dev) 83 { 84 /* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */ 85 dm_pci_clrset_config8(dev, GEN_PMCON_3, 3 << 4 | 1 << 10, 86 1 << 3 | 1 << 11 | 1 << 12); 87 /* Prepare sleep mode */ 88 clrsetio_32(ACPI_BASE_ADDRESS + PM1_CNT, SLP_TYP, SCI_EN); 89 90 /* Setup NMI on errors, disable SERR */ 91 clrsetio_8(0x61, 0xf0, 1 << 2); 92 /* Disable NMI sources */ 93 setio_8(0x70, 1 << 7); 94 /* Indicate DRAM init done for MRC */ 95 dm_pci_clrset_config8(dev, GEN_PMCON_2, 0, 1 << 7); 96 97 /* Clear status bits to prevent unexpected wake */ 98 setbits_le32(RCB_REG(0x3310), 0x0000002f); 99 clrsetbits_le32(RCB_REG(0x3f02), 0x0000000f, 0); 100 /* Enable PCIe Relaxed Order */ 101 setbits_le32(RCB_REG(0x2314), 1 << 31 | 1 << 7); 102 setbits_le32(RCB_REG(0x1114), 1 << 15 | 1 << 14); 103 /* Setup SERIRQ, enable continuous mode */ 104 dm_pci_clrset_config8(dev, SERIRQ_CNTL, 0, 1 << 7 | 1 << 6); 105 }; 106 107 static void pch_enable_ioapic(void) 108 { 109 u32 reg32; 110 111 /* Make sure this is a unique ID within system */ 112 io_apic_set_id(0x04); 113 114 /* affirm full set of redirection table entries ("write once") */ 115 reg32 = io_apic_read(0x01); 116 117 /* PCH-LP has 39 redirection entries */ 118 reg32 &= ~0x00ff0000; 119 reg32 |= 0x00270000; 120 121 io_apic_write(0x01, reg32); 122 123 /* 124 * Select Boot Configuration register (0x03) and 125 * use Processor System Bus (0x01) to deliver interrupts. 126 */ 127 io_apic_write(0x03, 0x01); 128 } 129 130 /* Enable all requested GPE */ 131 void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4) 132 { 133 outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0)); 134 outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32)); 135 outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_94_64)); 136 outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); 137 } 138 139 /* 140 * Enable GPIO SMI events - it would be good to put this in the GPIO driver 141 * but it would need a new driver operation. 142 */ 143 int enable_alt_smi(struct udevice *pch, u32 mask) 144 { 145 struct pch_lp_gpio_regs *regs; 146 u32 gpiobase; 147 int ret; 148 149 ret = pch_get_gpio_base(pch, &gpiobase); 150 if (ret) { 151 debug("%s: invalid GPIOBASE address (%08x)\n", __func__, 152 gpiobase); 153 return -EINVAL; 154 } 155 156 regs = (struct pch_lp_gpio_regs *)gpiobase; 157 setio_32(regs->alt_gpi_smi_en, mask); 158 159 return 0; 160 } 161 162 static int pch_power_options(struct udevice *dev) 163 { 164 int pwr_on_after_power_fail = MAINBOARD_POWER_OFF; 165 const char *state; 166 u32 enable[4]; 167 u16 reg16; 168 int ret; 169 170 dm_pci_read_config16(dev, GEN_PMCON_3, ®16); 171 reg16 &= 0xfffe; 172 switch (pwr_on_after_power_fail) { 173 case MAINBOARD_POWER_OFF: 174 reg16 |= 1; 175 state = "off"; 176 break; 177 case MAINBOARD_POWER_ON: 178 reg16 &= ~1; 179 state = "on"; 180 break; 181 case MAINBOARD_POWER_KEEP: 182 reg16 &= ~1; 183 state = "state keep"; 184 break; 185 default: 186 state = "undefined"; 187 } 188 dm_pci_write_config16(dev, GEN_PMCON_3, reg16); 189 debug("Set power %s after power failure.\n", state); 190 191 /* GPE setup based on device tree configuration */ 192 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), 193 "intel,gpe0-en", enable, ARRAY_SIZE(enable)); 194 if (ret) 195 return -EINVAL; 196 enable_all_gpe(enable[0], enable[1], enable[2], enable[3]); 197 198 /* SMI setup based on device tree configuration */ 199 enable_alt_smi(dev, fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 200 "intel,alt-gp-smi-enable", 0)); 201 202 return 0; 203 } 204 205 /* Magic register settings for power management */ 206 static void pch_pm_init_magic(struct udevice *dev) 207 { 208 dm_pci_write_config8(dev, 0xa9, 0x46); 209 clrbits_le32(RCB_REG(0x232c), 1), 210 setbits_le32(RCB_REG(0x1100), 0x0000c13f); 211 clrsetbits_le32(RCB_REG(0x2320), 0x60, 0x10); 212 writel(0x00012fff, RCB_REG(0x3314)); 213 clrsetbits_le32(RCB_REG(0x3318), 0x000f0330, 0x0dcf0400); 214 writel(0x04000000, RCB_REG(0x3324)); 215 writel(0x00041400, RCB_REG(0x3368)); 216 writel(0x3f8ddbff, RCB_REG(0x3388)); 217 writel(0x00007001, RCB_REG(0x33ac)); 218 writel(0x00181900, RCB_REG(0x33b0)); 219 writel(0x00060A00, RCB_REG(0x33c0)); 220 writel(0x06200840, RCB_REG(0x33d0)); 221 writel(0x01010101, RCB_REG(0x3a28)); 222 writel(0x040c0404, RCB_REG(0x3a2c)); 223 writel(0x9000000a, RCB_REG(0x3a9c)); 224 writel(0x03808033, RCB_REG(0x2b1c)); 225 writel(0x80000009, RCB_REG(0x2b34)); 226 writel(0x022ddfff, RCB_REG(0x3348)); 227 writel(0x00000001, RCB_REG(0x334c)); 228 writel(0x0001c000, RCB_REG(0x3358)); 229 writel(0x3f8ddbff, RCB_REG(0x3380)); 230 writel(0x0001c7e1, RCB_REG(0x3384)); 231 writel(0x0001c7e1, RCB_REG(0x338c)); 232 writel(0x0001c000, RCB_REG(0x3398)); 233 writel(0x00181900, RCB_REG(0x33a8)); 234 writel(0x00080000, RCB_REG(0x33dc)); 235 writel(0x00000001, RCB_REG(0x33e0)); 236 writel(0x0000040c, RCB_REG(0x3a20)); 237 writel(0x01010101, RCB_REG(0x3a24)); 238 writel(0x01010101, RCB_REG(0x3a30)); 239 dm_pci_clrset_config32(dev, 0xac, 0x00200000, 0); 240 setbits_le32(RCB_REG(0x0410), 0x00000003); 241 setbits_le32(RCB_REG(0x2618), 0x08000000); 242 setbits_le32(RCB_REG(0x2300), 0x00000002); 243 setbits_le32(RCB_REG(0x2600), 0x00000008); 244 writel(0x00007001, RCB_REG(0x33b4)); 245 writel(0x022ddfff, RCB_REG(0x3350)); 246 writel(0x00000001, RCB_REG(0x3354)); 247 /* Power Optimizer */ 248 setbits_le32(RCB_REG(0x33d4), 0x08000000); 249 /* 250 * This stops the LCD from turning on: 251 * setbits_le32(RCB_REG(0x33c8), 0x08000080); 252 */ 253 writel(0x0000883c, RCB_REG(0x2b10)); 254 writel(0x1e0a4616, RCB_REG(0x2b14)); 255 writel(0x40000005, RCB_REG(0x2b24)); 256 writel(0x0005db01, RCB_REG(0x2b20)); 257 writel(0x05145005, RCB_REG(0x3a80)); 258 writel(0x00001005, RCB_REG(0x3a84)); 259 setbits_le32(RCB_REG(0x33d4), 0x2fff2fb1); 260 setbits_le32(RCB_REG(0x33c8), 0x00008000); 261 }; 262 263 static int pch_type(struct udevice *dev) 264 { 265 u16 type; 266 267 dm_pci_read_config16(dev, PCI_DEVICE_ID, &type); 268 269 return type; 270 } 271 272 /* Return 1 if PCH type is WildcatPoint */ 273 static int pch_is_wpt(struct udevice *dev) 274 { 275 return ((pch_type(dev) & 0xfff0) == 0x9cc0) ? 1 : 0; 276 } 277 278 /* Return 1 if PCH type is WildcatPoint ULX */ 279 static int pch_is_wpt_ulx(struct udevice *dev) 280 { 281 u16 lpcid = pch_type(dev); 282 283 switch (lpcid) { 284 case PCH_WPT_BDW_Y_SAMPLE: 285 case PCH_WPT_BDW_Y_PREMIUM: 286 case PCH_WPT_BDW_Y_BASE: 287 return 1; 288 } 289 290 return 0; 291 } 292 293 static u32 pch_read_soft_strap(int id) 294 { 295 clrbits_le32(SPI_REG(SPIBAR_FDOC), 0x00007ffc); 296 setbits_le32(SPI_REG(SPIBAR_FDOC), 0x00004000 | id * 4); 297 298 return readl(SPI_REG(SPIBAR_FDOD)); 299 } 300 301 static void pch_enable_mphy(struct udevice *dev) 302 { 303 u32 data_and = 0xffffffff; 304 u32 data_or = (1 << 14) | (1 << 13) | (1 << 12); 305 306 data_or |= (1 << 0); 307 if (pch_is_wpt(dev)) { 308 data_and &= ~((1 << 7) | (1 << 6) | (1 << 3)); 309 data_or |= (1 << 5) | (1 << 4); 310 311 if (pch_is_wpt_ulx(dev)) { 312 /* Check if SATA and USB3 MPHY are enabled */ 313 u32 strap19 = pch_read_soft_strap(19); 314 strap19 &= ((1 << 31) | (1 << 30)); 315 strap19 >>= 30; 316 if (strap19 == 3) { 317 data_or |= (1 << 3); 318 debug("Enable ULX MPHY PG control in single domain\n"); 319 } else if (strap19 == 0) { 320 debug("Enable ULX MPHY PG control in split domains\n"); 321 } else { 322 debug("Invalid PCH Soft Strap 19 configuration\n"); 323 } 324 } else { 325 data_or |= (1 << 3); 326 } 327 } 328 329 pch_iobp_update(0xCF000000, data_and, data_or); 330 } 331 332 static void pch_init_deep_sx(bool deep_sx_enable_ac, bool deep_sx_enable_dc) 333 { 334 if (deep_sx_enable_ac) { 335 setbits_le32(RCB_REG(DEEP_S3_POL), DEEP_S3_EN_AC); 336 setbits_le32(RCB_REG(DEEP_S5_POL), DEEP_S5_EN_AC); 337 } 338 339 if (deep_sx_enable_dc) { 340 setbits_le32(RCB_REG(DEEP_S3_POL), DEEP_S3_EN_DC); 341 setbits_le32(RCB_REG(DEEP_S5_POL), DEEP_S5_EN_DC); 342 } 343 344 if (deep_sx_enable_ac || deep_sx_enable_dc) { 345 setbits_le32(RCB_REG(DEEP_SX_CONFIG), 346 DEEP_SX_WAKE_PIN_EN | DEEP_SX_GP27_PIN_EN); 347 } 348 } 349 350 /* Power Management init */ 351 static void pch_pm_init(struct udevice *dev) 352 { 353 debug("PCH PM init\n"); 354 355 pch_init_deep_sx(false, false); 356 pch_enable_mphy(dev); 357 pch_pm_init_magic(dev); 358 359 if (pch_is_wpt(dev)) { 360 setbits_le32(RCB_REG(0x33e0), 1 << 4 | 1 << 1); 361 setbits_le32(RCB_REG(0x2b1c), 1 << 22 | 1 << 14 | 1 << 13); 362 writel(0x16bf0002, RCB_REG(0x33e4)); 363 setbits_le32(RCB_REG(0x33e4), 0x1); 364 } 365 366 pch_iobp_update(0xCA000000, ~0UL, 0x00000009); 367 368 /* Set RCBA 0x2b1c[29]=1 if DSP disabled */ 369 if (readl(RCB_REG(FD)) & PCH_DISABLE_ADSPD) 370 setbits_le32(RCB_REG(0x2b1c), 1 << 29); 371 } 372 373 static void pch_cg_init(struct udevice *dev) 374 { 375 struct udevice *bus = pci_get_controller(dev); 376 u32 reg32; 377 u16 reg16; 378 ulong val; 379 380 /* DMI */ 381 setbits_le32(RCB_REG(0x2234), 0xf); 382 383 dm_pci_read_config16(dev, GEN_PMCON_1, ®16); 384 reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ 385 if (pch_is_wpt(dev)) 386 reg16 &= ~(1 << 11); 387 else 388 reg16 |= 1 << 11; 389 reg16 |= 1 << 5 | 1 << 6 | 1 << 7 | 1 << 12; 390 reg16 |= 1 << 2; /* PCI CLKRUN# Enable */ 391 dm_pci_write_config16(dev, GEN_PMCON_1, reg16); 392 393 /* 394 * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1 395 * RCBA + 0x2614[23:16] = 0x20 396 * RCBA + 0x2614[30:28] = 0x0 397 * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) 398 */ 399 clrsetbits_le32(RCB_REG(0x2614), 0x64ff0000, 0x0a206500); 400 401 /* Check for 0:2.0@0x08 >= 0x0b */ 402 pci_bus_read_config(bus, PCI_BDF(0, 0x2, 0), 0x8, &val, PCI_SIZE_8); 403 if (pch_is_wpt(dev) || val >= 0x0b) 404 setbits_le32(RCB_REG(0x2614), 1 << 26); 405 406 setbits_le32(RCB_REG(0x900), 0x0000031f); 407 408 reg32 = readl(RCB_REG(CG)); 409 if (readl(RCB_REG(0x3454)) & (1 << 4)) 410 reg32 &= ~(1 << 29); /* LPC Dynamic */ 411 else 412 reg32 |= (1 << 29); /* LPC Dynamic */ 413 reg32 |= 1 << 31; /* LP LPC */ 414 reg32 |= 1 << 30; /* LP BLA */ 415 if (readl(RCB_REG(0x3454)) & (1 << 4)) 416 reg32 &= ~(1 << 29); 417 else 418 reg32 |= 1 << 29; 419 reg32 |= 1 << 28; /* GPIO Dynamic */ 420 reg32 |= 1 << 27; /* HPET Dynamic */ 421 reg32 |= 1 << 26; /* Generic Platform Event Clock */ 422 if (readl(RCB_REG(BUC)) & PCH_DISABLE_GBE) 423 reg32 |= 1 << 23; /* GbE Static */ 424 if (readl(RCB_REG(FD)) & PCH_DISABLE_HD_AUDIO) 425 reg32 |= 1 << 21; /* HDA Static */ 426 reg32 |= 1 << 22; /* HDA Dynamic */ 427 writel(reg32, RCB_REG(CG)); 428 429 /* PCH-LP LPC */ 430 if (pch_is_wpt(dev)) 431 clrsetbits_le32(RCB_REG(0x3434), 0x1f, 0x17); 432 else 433 setbits_le32(RCB_REG(0x3434), 0x7); 434 435 /* SPI */ 436 setbits_le32(RCB_REG(0x38c0), 0x3c07); 437 438 pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); 439 } 440 441 static void systemagent_init(void) 442 { 443 /* Enable Power Aware Interrupt Routing */ 444 clrsetbits_8(MCHBAR_REG(MCH_PAIR), 0x7, 0x4); /* Fixed Priority */ 445 446 /* 447 * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU 448 * that BIOS has initialized memory and power management 449 */ 450 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3); 451 debug("Set BIOS_RESET_CPL\n"); 452 453 /* Configure turbo power limits 1ms after reset complete bit */ 454 mdelay(1); 455 456 cpu_set_power_limits(28); 457 } 458 459 static int broadwell_pch_init(struct udevice *dev) 460 { 461 int ret; 462 463 /* Enable upper 128 bytes of CMOS */ 464 setbits_le32(RCB_REG(RC), 1 << 2); 465 466 /* 467 * TODO: TCO timer halt - this hangs 468 * setio_16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT); 469 */ 470 471 /* Disable unused device (always) */ 472 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS); 473 474 pch_misc_init(dev); 475 476 /* Interrupt configuration */ 477 pch_enable_ioapic(); 478 479 /* Initialize power management */ 480 ret = pch_power_options(dev); 481 if (ret) 482 return ret; 483 pch_pm_init(dev); 484 pch_cg_init(dev); 485 systemagent_init(); 486 487 return 0; 488 } 489 490 static int broadwell_pch_probe(struct udevice *dev) 491 { 492 if (!(gd->flags & GD_FLG_RELOC)) 493 return broadwell_pch_early_init(dev); 494 else 495 return broadwell_pch_init(dev); 496 } 497 498 static int broadwell_pch_get_spi_base(struct udevice *dev, ulong *sbasep) 499 { 500 u32 rcba; 501 502 dm_pci_read_config32(dev, PCH_RCBA, &rcba); 503 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ 504 rcba = rcba & 0xffffc000; 505 *sbasep = rcba + 0x3800; 506 507 return 0; 508 } 509 510 static int broadwell_set_spi_protect(struct udevice *dev, bool protect) 511 { 512 return lpc_set_spi_protect(dev, BIOS_CTRL, protect); 513 } 514 515 static int broadwell_get_gpio_base(struct udevice *dev, u32 *gbasep) 516 { 517 dm_pci_read_config32(dev, GPIO_BASE, gbasep); 518 *gbasep &= PCI_BASE_ADDRESS_IO_MASK; 519 520 return 0; 521 } 522 523 static const struct pch_ops broadwell_pch_ops = { 524 .get_spi_base = broadwell_pch_get_spi_base, 525 .set_spi_protect = broadwell_set_spi_protect, 526 .get_gpio_base = broadwell_get_gpio_base, 527 }; 528 529 static const struct udevice_id broadwell_pch_ids[] = { 530 { .compatible = "intel,broadwell-pch" }, 531 { } 532 }; 533 534 U_BOOT_DRIVER(broadwell_pch) = { 535 .name = "broadwell_pch", 536 .id = UCLASS_PCH, 537 .of_match = broadwell_pch_ids, 538 .probe = broadwell_pch_probe, 539 .ops = &broadwell_pch_ops, 540 }; 541