1 /* 2 * Copyright (C) 2011 The Chromium Authors 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <asm/arch/iomap.h> 11 #include <asm/arch/pch.h> 12 13 static int broadwell_northbridge_early_init(struct udevice *dev) 14 { 15 /* Move earlier? */ 16 dm_pci_write_config32(dev, PCIEXBAR + 4, 0); 17 /* 64MiB - 0-63 buses */ 18 dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1); 19 20 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); 21 dm_pci_write_config32(dev, DMIBAR, DMI_BASE_ADDRESS | 1); 22 dm_pci_write_config32(dev, EPBAR, EP_BASE_ADDRESS | 1); 23 writel(EDRAM_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + EDRAMBAR); 24 writel(GDXC_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + GDXCBAR); 25 26 /* Set C0000-FFFFF to access RAM on both reads and writes */ 27 dm_pci_write_config8(dev, PAM0, 0x30); 28 dm_pci_write_config8(dev, PAM1, 0x33); 29 dm_pci_write_config8(dev, PAM2, 0x33); 30 dm_pci_write_config8(dev, PAM3, 0x33); 31 dm_pci_write_config8(dev, PAM4, 0x33); 32 dm_pci_write_config8(dev, PAM5, 0x33); 33 dm_pci_write_config8(dev, PAM6, 0x33); 34 35 /* Device enable: IGD and Mini-HD */ 36 dm_pci_write_config32(dev, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN); 37 38 return 0; 39 } 40 41 static int broadwell_northbridge_probe(struct udevice *dev) 42 { 43 if (!(gd->flags & GD_FLG_RELOC)) 44 return broadwell_northbridge_early_init(dev); 45 46 return 0; 47 } 48 49 static const struct udevice_id broadwell_northbridge_ids[] = { 50 { .compatible = "intel,broadwell-northbridge" }, 51 { } 52 }; 53 54 U_BOOT_DRIVER(broadwell_northbridge_drv) = { 55 .name = "broadwell_northbridge", 56 .id = UCLASS_NORTHBRIDGE, 57 .of_match = broadwell_northbridge_ids, 58 .probe = broadwell_northbridge_probe, 59 }; 60